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Low-static-power current-mode band-gap reference voltage circuit

A low static power consumption, reference voltage technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve problems such as large static power consumption, and achieve the effect of reducing static power consumption

Inactive Publication Date: 2013-07-10
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0025] Aiming at the problem that the traditional current mode reference voltage has relatively large static power consumption, the present invention provides a current mode bandgap reference voltage circuit with low static power consumption. The grounding resistor is reconnected to the reference voltage output terminal, so that the current of each branch in the circuit can be fully utilized, reducing unnecessary quiescent current, and significantly reducing the static power consumption of the current mode reference voltage

Method used

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  • Low-static-power current-mode band-gap reference voltage circuit
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  • Low-static-power current-mode band-gap reference voltage circuit

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Embodiment Construction

[0033] The principles and features of the present invention will be described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0034] see figure 2 , the current mode bandgap reference voltage circuit with low static power consumption of the present invention is based on the traditional bandgap reference voltage circuit, comprising PNP transistors Q1 and Q2, PMOS transistors M1, M2 and M3, operational amplifier OP, resistor R 1 , R 2 , R 3 , R 4 ; The bases and collectors of the PNP transistors Q1 and Q2 are grounded, and the emitter of the PNP transistor Q1 passes through the resistor R 2 With the non-inverting input terminal of the operational amplifier OP and the drain of the PMOS transistor M1, the resistor R 1 Connected at one end, the resistor R 1 The other end is grounded, the emitter of the PNP transistor Q2 is connected to...

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Abstract

A low-static-power current-mode band-gap reference voltage circuit is based on the basis of a traditional band-gap reference voltage circuit which is provided with two PNP audions Q1 and Q2, three PMOS (positive channel metal oxide semiconductor) transistors M1, M2 and M3, an operational amplifier OP and four resistors R1, R2, R3 and R4. The low-static-power current-mode band-gap reference voltage circuit is characterized by subjecting the traditional band-gap reference voltage circuit to improvements which comprise removing R1 and R3 and additionally and respectively arranging two resistors R5 and R6 between the non-inverting input end of the operational amplifier OP and the drain electrode of the PMOS transistor M3 and between the inverting input end of the operational amplifier OP and the drain electrode of the PMOS transistor M3, wherein the resistance value of the R5 is equal to that of R6. Under the conditions of the same power voltage and the same bias currents of the audions Q1 and Q2, the total static power of the low-static-power current-mode band-gap reference voltage circuit is 70% lower than that of the traditional band-gap reference voltage circuit when the output reference voltage is 1 volt.

Description

technical field [0001] The invention relates to a bandgap reference voltage circuit, in particular to a current-mode bandgap reference voltage circuit with low static power consumption, belonging to the technical field of bipolar transistor (BJT) and metal oxide semiconductor (MOS) transistor integrated circuits. Background technique [0002] In the prior art, there is a figure 1 The traditional bandgap reference voltage circuit shown includes PNP transistors Q1 and Q2, PMOS transistors M1, M2 and M3, operational amplifier OP, and resistor R 1 , R 2 , R 3 , R 4 ; The base and collector of Q1 and Q2 are grounded, and the emitter of Q1 passes through the resistor R 2 It is connected with the non-inverting input terminal of the operational amplifier OP and the drain of the PMOS transistor M1 and marked as node A, and the resistor R 1 Connected between node A and ground, the emitter of Q2 is connected to the inverting input terminal of the operational amplifier OP and the d...

Claims

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Application Information

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IPC IPC(8): G05F3/26
Inventor 祝靖张学永张允武宋慧滨孙伟锋陆生礼时龙兴
Owner SOUTHEAST UNIV
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