Bilayer gate dielectric with low equivalent oxide thickness for graphene devices

A graphene layer, double-layer gate technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, nanotechnology for materials and surface science, etc., can solve problems such as expensive equipment

Inactive Publication Date: 2013-08-14
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, a significant amount of time may be required to design such a scaled-down transistor
Moreover, the equipment necessary to produce such devices can be expensive, and / or the processes associated with producing such devices must be strictly controlled and / or operated under specific conditions
Therefore, there are substantial costs associated with quality control of semiconductor manufacturing

Method used

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  • Bilayer gate dielectric with low equivalent oxide thickness for graphene devices
  • Bilayer gate dielectric with low equivalent oxide thickness for graphene devices
  • Bilayer gate dielectric with low equivalent oxide thickness for graphene devices

Examples

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example 1

[0064] This example provides a graphene-containing structure comprising an underlying graphene layer with overlying HfO 2 between SiN layers. The structure is prepared by first providing a SiC base substrate and then epitaxially growing a graphene layer on the uppermost surface of the base substrate. The graphene layer is formed using the annealing treatment mentioned in the above detailed description of the present disclosure. After disposing a graphene layer on top of the SiC base substrate, a 2 nm thick stretched SiN layer was formed by PECVD at 400°C. Next, a 10 nm thick HfO was formed by ALD on top of the SiN layer 2 layer.

[0065] Figure 9A is an actual AFM height image of the structure after forming a SiN layer on top of the graphene layer according to this example of the present disclosure. The Z scale in nm is shown on the right. The different terrain heights of this image are indicated by the different shading corresponding directly to the shaded z-scale bar ...

example 2

[0070] This example provides a graphene-containing structure where HfO 2 layer is formed directly on the uppermost surface of the graphene layer. The structure is prepared by first providing a SiC base substrate and then epitaxially growing a graphene layer on the uppermost surface of the base substrate. The graphene layer is formed using the annealing treatment mentioned in the above detailed description of the present disclosure. After disposing a graphene layer on top of the SiC base substrate, a 10-nm-thick HfO layer was formed directly on the uppermost surface of the graphene layer by ALD. 2 layer.

[0071] Figure 13 is the direct formation of HfO on top of the graphene layer according to the present example of the disclosure 2 Actual AFM height image of the structure after the layer. The Z scale is shown on the right. Figure 14 is an example of HfO formed directly on top of a graphene layer 2 Cross-sectional AFM image of layer roughness.

[0072] SEM and AFM pr...

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Abstract

A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.

Description

technical field [0001] The present disclosure relates to semiconductor structures and methods of fabrication thereof. More particularly, the present disclosure relates to semiconductor structures including a double-layer gate dielectric formed atop graphene with a low equivalent oxide thickness (EOT) and methods of forming the same. Background technique [0002] Several trends currently exist in the semiconductor and electronics industries, including, for example, devices being made smaller, faster and requiring less energy than previous generations of devices. One reason for these trends is because personal devices, such as cellular telephones and personal computing devices, are being made smaller and more portable. In addition to becoming smaller and more portable, personal devices also require increased memory, greater computing power and speed. In view of these continuing trends, there is an increasing demand in the industry for smaller and faster transistors to provid...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/51H01L29/10H01L21/336H01L21/285
CPCH01L29/778H01L21/02527H01L29/78684H01L29/1606H01L29/66045H01L21/02378H01L21/02617H01L21/0237B82Y40/00H01L29/4908B82Y30/00H01L29/7781H01L21/02661H01L29/513
Inventor C·D·迪米特罗普洛斯D·B·法默A·格里尔林佑民D·A·诺伊迈尔D·法伊弗朱文娟
Owner IBM CORP
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