Scenario-based processor system-level verification completeness measurement method

Abstract

The invention discloses a scenario-based processor system-level verification completeness measurement method. The method includes 1), constructing typical application scenarios according to the application field of a processor; 2), constructing scenario testing environment for each application scenario to allow a scenario testing case to test the processor, generating scenario reliability according to test completion state, and taking a weighted average of scenario reliability of all the application scenarios as a system-level verification completeness measurement value; determining whether the completeness of the processor meets the processing requirements of the processor or not according to the system-level verification completeness measurement value; if not, returning to step 2) to test low-reliability application scenarios continuously; and if so, completing test and exiting. According to the scenario-based processor system-level verification completeness measurement method, basis is provided for processing through quantitative description of related verification reliability of the processor, and the scenario-based processor system-level verification completeness measurement method has the advantages of high verification speed, high verification efficiency, high testing environment utilization rate, and short verification time.

Description

technical field [0001] The invention relates to the field of correctness verification of processor design, in particular to a scenario-based method for measuring the completeness of processor system-level verification. Background technique [0002] In the processor design process, a very critical issue is how to confirm the correctness of the design. Due to the complexity of the design of modern general-purpose processors, the verification process is further complicated. Intel's Pentium4 processor has more than 1 million lines of code and nearly 42M transistors. There are nearly 70 people in its functional verification team, and the verification period from full-chip code stabilization to wafer release is nearly 3 years (1997-1999), and it took nearly 10 months to perform post-silicon wafer verification after wafer release. Although SoC (System-on-a-Chip, also known as system on chip) technology has greatly reduced the design and verification complexity of general-purpose ...

AI Technical Summary

Problems solved by technology

The actual situation is that the coverage test of each component of the processor cannot be carried out in the system-level verification stage, and the coverage test is not a problem that should be considered or cannot be considered in the system-level verification

Images