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Inductor for post passivation interconnect

A post-passivation interconnection, inductor technology, applied in the direction of inductors, electrical solid devices, circuits, etc., can solve the problems of complex process, large chip area, limitation or constraint pursuit, etc.

Active Publication Date: 2013-09-18
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the UTM process is very complex and requires a large chip area
Additionally, UTM processing may limit or constrain the pursuit of a high figure of merit

Method used

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  • Inductor for post passivation interconnect
  • Inductor for post passivation interconnect
  • Inductor for post passivation interconnect

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Embodiment Construction

[0035] The making and using of the presently preferred embodiments are discussed in detail below. It will be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0036] The invention will be described with respect to preferred embodiments in a specific context, namely an inductor device. However, the invention is also applicable to other semiconductor structures or circuits.

[0037] Also refer to Figure 1-Figure 2 , an embodiment of the inductor device 10 is described. As explained more fully below, Figure 1-Figure 2 The inductor device 10 provides good shielding against electromagnetic interference and a high quality factor Q. The inductor device 10 generally includes a post passivation interconnect (PPI) layer 12 and...

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Abstract

An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member. The invention also provides an inductor for post passivation interconnect.

Description

technical field [0001] The present invention relates to the field of semiconductors, and more particularly, the present invention relates to an inductor for post-passivation interconnection. Background technique [0002] Advances in the performance of semiconductor devices are largely attributable to the reduction in device size. Initially, lithography and other microelectronics fabrication techniques capable of scaling such devices could not modify the inductors, capacitors and other passive components typically employed in semiconductor devices. However, the resulting developed inductor design similarly exploits advances in microelectronics fabrication processes and undergoes scaling to a degree similar to active devices. [0003] By way of example, inductors are now typically created on the surface of a semiconductor device substrate in a helical shape created in a plane parallel to the substrate surface. An inductor may have a plurality of these helical coils when a su...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522H01L23/552H01L21/02H10N97/00
CPCH01L23/552H01L28/10H01L23/585H01L24/11Y10T29/4902H01L2224/0401H01L23/5225H01L23/5227H01L2224/02351H01L27/02H01L21/768H01L24/03H01L2224/06515
Inventor 蔡豪益陈宪伟郭鸿毅陈洁陈英儒于宗源
Owner TAIWAN SEMICON MFG CO LTD