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Timing calibration circuit for time-interleaved analog-to-digital converter and method

An analog-to-digital, timing correction technology, applied in analog/digital conversion calibration/test, analog/digital conversion, code conversion, etc., can solve problems such as drop

Active Publication Date: 2013-09-18
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the time sequence of the time-interleaved analog-to-digital converter is inconsistent (timing mismatch), it will seriously directly lead to a decrease in the signal noise ratio (Signal Noise Ratio, SNR)

Method used

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  • Timing calibration circuit for time-interleaved analog-to-digital converter and method
  • Timing calibration circuit for time-interleaved analog-to-digital converter and method
  • Timing calibration circuit for time-interleaved analog-to-digital converter and method

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no. 1 example

[0045] Please also refer to figure 1 and figure 2 , figure 1 Shown as a partial schematic diagram of a time-interleaved analog-to-digital converter, figure 2 Shown is a flow chart of a time-interleaved analog-to-digital converter timing correction method. The time-interleaved A / D converter 1 includes a plurality of A / D converters and a timing correction circuit 12. For convenience of description, the analog-digital converters in the following embodiments are illustrated by taking the analog-digital converter 11(i-1), the analog-digital converter 11(i), and the analog-digital converter 11(i+1) as examples. However, it is not limited to this, and those skilled in the art should flexibly adjust the number of analog-digital converters according to their applications. The analog-digital converter 11(i-1), the analog-digital converter 11(i) and the analog-digital converter 11(i+1) are respectively controlled by the clock signal ψ i-1 , Clock signal ψ i Clock signal ψ i+1 The analog...

no. 2 example

[0059] Please refer to Picture 9 , Picture 9 Shown is a block diagram of a timing correction circuit according to the second embodiment. The main difference between the second embodiment and the first embodiment is that the timing correction circuit 12(2) further includes a coefficient variation detection circuit 124 in addition to the correlation unit 121, the adaptive filter 122, and the delay unit 123. The coefficient variation detection circuit 124 detects the coefficient variation ε i , And the coefficient variation ε i When it is less than a threshold value, the adaptive filter 122 is controlled to stop the operation to save power consumption. Conversely, when the coefficient variation ε i When it is not less than a threshold value, the adaptive filter 122 is controlled to perform operations again.

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Abstract

A timing calibration circuit and a timing calibration method for a time-interleaved analog-to-digital converter (ADC) are provided. The timing calibration circuit includes a correlation unit, an adaptive filter and a delay cell. The correlation unit generates a first correlation coefficient according to a first zero-crossing possibility distribution between a first digital data and a second digital data, and generates a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and a third digital data. The adaptive filter generates a predicted time skew according to a difference between the first correlation coefficient and the second correlation coefficient. The delay cell calibrates a clock signal of the ADC according to the predicted time skew.

Description

Technical field [0001] The invention relates to an analog-to-digital converter, and more particularly to a timing correction circuit and a timing correction method of a time-interleaved analog-digital converter. Background technique [0002] In the current analog-to-digital converter architecture, Flash ADC and Time-interleaved ADC are the fastest. However, for applications in high-speed processing, the area and power consumption of flash analog-to-digital converters will increase exponentially with the increase in sampling frequency and resolution. Digitizers are easier to achieve high-speed purposes. However, when the timing mismatch of the time-interleaved analog-to-digital converter is inconsistent, it will seriously directly cause the signal-to-noise ratio (Signal Noise Ratio, SNR) to drop. And as the operating speed is higher, the impact will be more severe. In view of this, how to improve the timing inconsistency of the time-interleaved analog-to-digital converter and i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1009H03M1/1215
Inventor 陈俊仁蔡宗亨汤子仪
Owner IND TECH RES INST
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