Modeling method of interconnection structure and automatic generation method of interconnection resource allocation vector

Abstract

The interconnection structure modeling method and the interconnection resource allocation vector automatic generation method belong to the FPGA technology. The interconnection structure modeling method of the present invention includes the following steps: first classify the metal wires in the chip, the metal wires of the same type are collectively called a layer, and only the programmable configuration point PIP in the switch box is used between the two metal wires. In order to establish a connection, the PIP between the same metal lines is called intra-PIP, and the PIP between different metal lines is called inter-PIP; then all layers are used as points, and the connection relationship of PIPs is used as edges to establish a graph. The invention can automatically generate test configurations and has high test efficiency. The present invention has a high test coverage rate for interconnection resources, especially for PIP coverage. The invention is not aimed at a specific type of FPGA, but can be used for SRAM-type FPGA testing, has good versatility and is convenient for transplantation. The invention can achieve more accurate fault location and diagnosis.

Description

technical field [0001] The invention belongs to FPGA technology. Background technique [0002] The SRAM type Field Programmable Gate Array (Field Programmable Gate Array, hereinafter referred to as FPGA) is mainly composed of a programmable logic cell array, input and output modules, intellectual property cores, and a large number of interconnect resources (InterconnectResource, hereinafter referred to as IR). [0003] In the SRAM-based FPGA interconnection resource test, due to the variety of interconnection resources, the connection relationship is complex and changeable, and the interconnection lines and Programmable InterconnectPoint (PIP) are inside the chip, occupying a large chip area, the test has been is a difficult problem to solve. [0004] With the development of modern FPGAs, interconnect resources are becoming more and more complex, and their proportion in FPGAs is increasing, and even close to 90% of FPGAs with tens of millions of gates, so the probability of...

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Problems solved by technology

The method of the literature (Application-IndependentTestingofFPGAInterconnects) and the literature (Shenyang Institute of Automation, Chinese Academy of Sciences. An FPGA testing method based on the maximum flow method [P]. Invention patent, CN102116839A, 2011-07-06) can only do global testing, not Partially tested, and poor test coverage for PIP

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