Deep groove manufacturing method used in mems process
A manufacturing method and deep groove technology, which are applied in the process of producing decorative surface effects, manufacturing microstructure devices, metal material coating processes, etc., can solve problems such as inability to form U-shaped grooves, and achieve high aspect ratio, CMOS Process-compatible, low-cost effects
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0038] Below to figure 1 The production process shown as an example, combined with the attached Figures 2a to 2j , a detailed description of a deep trench manufacturing method used in MEMS technology.
[0039] In step S1, first, see Figure 2a A buffer layer 101 is respectively formed on the front and back sides of a silicon substrate 100 for MEMS capping. Wherein, the silicon substrate 100 is a p-type doped silicon wafer with a certain concentration. The material of the buffer layer 101 is silicon dioxide (SiO2), the buffer layer 101 is formed by thermal oxidation, and the thickness of the buffer layer is about
[0040] Second, see Figure 2b , on the surface of each buffer layer 101 that has been formed, a masking layer 102 with a certain thickness is deposited by using a low pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition System, LPCVD), and the thickness of the masking layer 102 is about The material used for the masking layer 102...
Embodiment 2
[0054] The following takes the production process shown in Figure 2 as an example, combined with the attached Figures 2a to 2h and combine Figure 2k and 2l , another deep trench fabrication method used in MEMS technology is described in detail.
[0055] In this embodiment, for the specific content of step S1 to step S4, please refer to the content of step S1 to step S4 in the first embodiment, respectively, and details will not be repeated here.
[0056] In step S5, first, see Figure 2k , taking advantage of the feature that the porous silicon layer is easy to oxidize, adopting a thermal oxidation process to make the porous silicon layer D3 into a thermal silicon oxide layer 106'.
[0057] Wherein, when the contact layer 104 is formed by implanting B ions into the back side of the silicon substrate 100, a thermal silicon oxide layer 106' is also formed on the back side of the silicon substrate; when the contact layer 104 is In the case of an aluminum layer, there is no ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More - R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com
