Bus architecture for multiprocessor parallel communication

A multi-processor and communication bus technology, which is applied in the field of multi-processor parallel communication bus architecture, can solve communication problems and other problems, achieve the effect of maximizing investment benefits, improving communication efficiency, and saving R&D investment

Inactive Publication Date: 2014-01-01
XUJI GRP +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a bus architecture for multiprocessor parallel communication, to solve the communication problem between each CPU in the existing multiprocessor parallel processing application

Method used

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  • Bus architecture for multiprocessor parallel communication
  • Bus architecture for multiprocessor parallel communication
  • Bus architecture for multiprocessor parallel communication

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Embodiment 1

[0013] Serial bus: As the speed of the parallel bus increases, the problem of crosstalk between lines becomes more prominent. In recent years, with the development of high-speed serial communication technology, from the early RS485 up to 10M to the current LVDS close to 2G, the serial communication rate has been greatly improved, and the serial communication bus has also emerged.

[0014] The serial bus of the bus architecture of the multiprocessor parallel communication adopts the serial bus technology of multi-transmitting nodes, which can realize one transmission and multiple receptions, and the maximum rate can reach 500Mbps. In this structure, multiple transceivers can be connected to the same bus, such as figure 1 As shown, the sending and receiving state can be controlled by controlling the sending and receiving direction, thus allowing two-way half-duplex communication.

[0015] The bus architecture of multiprocessor parallel communication, the communication bus inclu...

Embodiment 2

[0020] Such as image 3 As shown, in order to further mitigate bus contention, the figure 2 The shown multi-processor parallel communication bus architecture is based on a plurality of serial buses, and a parallel bus is also provided. The parallel bus is N sections of sub-buses arranged in parallel, and each section of sub-buses is connected to at least one CPU plug-in.

[0021] The traditional shared parallel bus is segmented (divided into 3 segments), and each segment is a fully functional parallel bus backplane structure, forming a segmented multi-bus architecture from the perspective of the overall chassis.

[0022] In the application of HVDC power transmission system, it is most common that there are less than or equal to 3 CPUs in one chassis. Then, if a high-speed parallel bus is divided into three parallel buses, most of the application needs will be met. Of course, a spare sub-bus can also be added for use when more processors are used. Physically speaking, if the...

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Abstract

The invention relates to a bus architecture for multiprocessor parallel communication. The bus architecture for the multiprocessor parallel communication comprises a communication bus communicated with central processing unit (CPU) plugins, wherein the communication bus comprises M serial channels, each CPU plugin is provided with at least M communication interfaces, and the communication interfaces of the CPU plugins are connected with the serial channels in a one-to-one correspondence mode. The bus architecture adopts a total-exchange serial bus which is substantially of a multiple-transmitting-receiving-node serial bus structure and used for multiprocessor data exchange. Therefore, the communication problem of an arbitrary number of slot position processors is solved, meanwhile the communication efficiency of the processors is improved, and multi-task and multiple-CPU parallel processing application with high real-timeliness requirement is met. The bus architecture for the multiprocessor parallel communication has good continuity and forward compatibility technically, subsequent investment in research and development can be saved, only CPU and backboards are locally required to be changed, other types of IO plugins are not required to be changed, and therefore the investment benefit can be maximized.

Description

technical field [0001] The invention relates to a bus architecture for multiprocessor parallel communication. Background technique [0002] The control and protection platform is the core equipment of the secondary side of the converter station of the direct current transmission project, and is the nerve center of the direct current transmission control and protection system. In HVDC power transmission projects, the control and protection platform is used in many occasions such as station control, pole control, valve group control, AC and DC protection, etc. To sum up their common characteristics, they are all multi-processor parallel processing applications, that is, according to the complexity of the application, several CPUs are configured in one chassis, and each CPU is combined with the corresponding peripheral I / O plug-in to form multiple CPUs with specific functions. processing collection. But in the traditional design, all CPUs and peripheral plug-ins in a chassis ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/17
Inventor 李延龙蒋大海李宝香张宝华吴述超魏民权侯林杰
Owner XUJI GRP
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