7 results about "Bus contention" patented technology

The application discloses an IO module communication control method based on master-slave cooperation and relates to the technical field of industrial automation control.The application realizes a double-mode autonomous reporting mechanism of periodic reporting and state change triggering by maintaining an analog-digital counter and a feature pair in a slave station,significantly reduces the response delay of input state change,avoids the waste of bus bandwidth caused by invalid period reporting,substantially improves the throughput capacity of a multi-slave bus system on the premise of ensuring real-time performance,and realizes fair and efficient bus competition resolution without intervention of a master station based on a bit-by-bit arbitration mechanism of an open-drain bus.

This invention provides a three-dimensional force data management method and system, relating to the management and communication of three-dimensional force data from tactile sensors. The method quantizes and compresses the X / Y / Z axis amplitudes of each three-dimensional force vector to 10 bits, and separately encodes the X and Y sign bits into 2 bits, forming a compact 32-bit representation of 10+10+10+2 bits. At the transmitting end, continuous three-dimensional force vector arrays are batch-packed into multiple 64-byte communication frames with 32-bit alignment and zero-copy, and then sent. At the receiving end, the three-axis force and direction information is quickly recovered through bitmasking and shifting. Simultaneously, addressing the bus contention problem caused by multiple nodes powering on in parallel, this invention utilizes a unique chip identifier and a hardware counter to generate multi-level random startup delays, enabling staggered initialization and transmission by multiple devices, thereby reducing frame loss and congestion. This invention has the advantages of data compression, fast parsing, low memory and bandwidth consumption, and high stability across multiple nodes, making it suitable for mass production deployment of tactile sensor products using real-time buses such as CAN / CAN-FD.

The application discloses a soft and hard cooperative optimization method of a large model multi-directory isolation scheduling architecture, and is based on an original multi-directory level isolation safety management and control architecture and a no-bypass full-process management and control module. The hardware layer realizes no-conflict autonomous optimization through on-chip firmware exclusive configuration permission. The on-chip integrated multi-dimensional sensor, the clock management unit and the storage controller complete advanced fault tolerance such as junction temperature timing compensation, firmware-level power gating and storage bad block mapping. The software layer completes full-dimensional lightweight performance optimization according to the multi-directory independent permission domain thread level isolation queue at the only compliance execution opportunity, and the software and hardware have no bus competition and deep cooperation.

The application provides a multi-path device synchronous read-write method and system, relates to the technical field of multi-path synchronous read-write operation monitoring, and realizes intelligent identification and intervention on device read-write conflicts by array arrangement on the multi-path device, collection of first state data sets and second state data sets of the device, calculation of addressing interference coefficients Xzr i of the i-th device and array conflict scheduling cost coefficients Cb i , and accurate evaluation of synchronous scheduling risks. After the execution of the scheduling strategy, the system further realizes real-time perception of fine-grained data interference based on page block heat tracking and adjacent page disturbance analysis, and dynamically triggers a hot data migration strategy, so that the read disturbance between devices and bus contention are effectively reduced, and the overall read-write efficiency and data consistency are improved. The system is particularly suitable for high-concurrency, distributed storage and high-reliability scenarios.

The application provides a bus communication system and method based on a compound wing unmanned aerial vehicle power system, which comprises a bus repeater, a standard bus interface module, a double bus communication protocol module and a bus topology structure module; the bus repeater comprises a data transceiving module, a data processing module and a data storage module; the data transceiving module comprises a non-isolation unit and an isolation unit; the non-isolation unit is connected with a flight control navigation system; the isolation unit is connected with the standard bus interface module; the double bus communication protocol module comprises a bus competition processing protocol unit, a data analysis and distribution protocol unit and a fault processing protocol unit; the bus topology structure module adopts a tree topology and comprises a main bus and a plurality of branch buses; and the application can realize safe and efficient transmission of data between the power system and the flight control navigation system, improve the anti-interference ability, expandability and fault tolerance of the system.

The application provides a mixed test system, method, electronic equipment and storage medium of a multi-core heterogeneous system-level chip, the mixed test system comprising: a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller and a plurality of data network encapsulators; the protocol conversion gateway device comprising a bus slave interface, a storage buffer unit and a flow control state machine. Through the mixed test system architecture of the serial control network component configuration, the protocol conversion gateway device multiplexing and the local test distribution dedicated network, the inherent contradictions of the prior art in time, cost and contention are cooperatively solved in the multi-core heterogeneous system-level chip, the flexibility and scalability of testing the multi-core heterogeneous system-level chip are improved, the hardware cost and wiring congestion are significantly reduced, the bus contention is eliminated, the test efficiency is improved and the time cost of parallel testing is reduced.

The invention provides a hybrid test system and method for a multi-core heterogeneous system-on-chip, electronic equipment and a storage medium. The hybrid test system comprises a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller and a plurality of data network encapsulators, the protocol conversion gateway device comprises a bus slave interface, a storage buffer unit and a flow control state machine. Through a hybrid test system architecture of serial control network component configuration, protocol conversion gateway device multiplexing and local test distribution private network, inherent contradictions in the aspects of time, overhead and contention in the prior art are collaboratively solved in a multi-core heterogeneous system-on-chip; compared with the prior art, the method has the advantages that the flexibility and expandability of testing the multi-core heterogeneous system-on-chip are improved, the hardware overhead and wiring congestion are remarkably reduced, the bus contention is eliminated, the testing efficiency is improved, and the time overhead of parallel testing is reduced.