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86 results about "Cost burden" patented technology

The burden rate consists of indirect costs associated with employees, over and above gross compensation or payroll costs. Typical costs associated with the burden rate include payroll taxes, workers' compensation and health insurance, paid time off, training and travel expenses, vacation and sick leave,...

Indoor positioning method and system based on signal multipath propagation measurement

ActiveCN110351655AHigh accuracy of pseudo-range measurementExcellent theoretical distance measurement accuracyParticular environment based servicesPosition fixationCost burdenOperational costs
The invention discloses an indoor positioning method and system based on signal multipath propagation measurement, and the method comprises the following steps: S1, determining an available signal source and the coordinates of the available signal source from a plurality of indoor signal sources; S2, obtaining the distance from the mobile terminal to the available information source; S3, acquiringa current coordinate of the mobile terminal based on the distance; S4, enabling the mobile terminal to execute positioning display on an electronic map based on the coordinates; and S5, executing training of a channel environment fingerprint analysis engine based on the available information source and the coordinates of the mobile terminal. The technical scheme has the beneficial effects that the precision of measuring the pseudo distance between the mobile terminal and the available information source is high; positioning is realized by adopting public visible base stations and public visible radio signals, such as LBS, WiFi, WiMAX, FM, ZigBee and other fixed base station signals, access authorization of a base station owner is not needed, infrastructure construction investment and energy consumption are not increased, and operation cost burden is not increased.
Owner:BORUITAIKE SCI & TECH NINGBO CO LTD

Suction and release double paper mechanism of sticky handle paper cup forming machine

A double paper piece absorbing and releasing mechanism for a pasted handle type paper cup forming machine comprises an absorbing and releasing structure and a stacking structure. A cam rocker drive mechanism is connected with a connecting rod to form the absorbing and releasing structure, the connecting rod is movably connected upwards with a sliding plate, rollers and pins, the sliding plate is sequentially connected upwards with a pipe seat, suction pipes and suction nozzles, and a paper frame plate is arranged above the suction nozzles. The stacking structure mainly comprises the paper frame plate, a paper frame strip, a support leg, a blowing seat, a blowing pipe, a horizontal shaft, a support rod, a frame leg, paper stoppers, paper blocking rods and the like. The paper blocking rods are arranged on the peripheries of a front opening and a rear opening of the paper frame plate, and each paper blocking rod is used for blocking double paper pieces. The double paper piece absorbing and releasing mechanism has the advantages that the double paper pieces are stacked by the aid of a single paper frame, a single cam rocker drives two groups of suction nozzles to move, a paper cup with a handle can be produced once, the problem that the paper cup is too hot to handle is solved, and the cost burden of secondary manufacture is relieved.
Owner:瑞安市胜利机械有限公司

Communication network congestion control method

InactiveCN101296187AOmit the traffic shaping moduleReduce cost burdenData switching networksTraffic capacityCost burden
The invention discloses a congestion control method for a communication network, which pertains to the field of network communication. The method comprises the following steps: when a certain information source point excessively sends data and one or more congestion points are caused in the communication network; each congestion point can generate a series of congestion events which drive a preset responsibility point calculating process. A responsibility point R of the information source point is obtained when the calculation of the time span of a T tempo is accumulated; during a preset appraisal period, the responsibility point R of every T tempo is accumulated, and a total responsibility point U of the information source point is obtained; according to the total responsibility point U and a preset punishing strategy, punishment with sufficient strength is carried out to the information source point so as to force the information source point to limit flow consciously. By establishing a supervision mechanism, the method causes the information source point to limit flow consciously, thus saving a flow shaping module at the edge port of the communication network, eliminating the main cost burden for the whole network to realize congestion control and remarkably lowering realizing cost for promising the communication network of QoS as a whole.
Owner:BEIJING YICHEN COMM TECH INST

Imaging box chip, multifunctional writer, and imaging box chip processing device and method

The invention relates to an imaging box chip processing device. The imaging box chip processing device comprises a multifunctional writer and an imaging box chip; the multifunctional writer is used for storing various groups of program information and various groups of data information, and determining the model number of the imaging box chip, or further used for writing a corresponding group of program information and/or a corresponding group of data information to the imaging box chip according to the determined model number; the various groups of program information include various groups of complete communication protocols corresponding to the communication of the imaging box chip with imaging devices of different types; the various groups of data information include various groups of chip data information corresponding to the imaging box chips of different types; the imaging box chip is used for recording the program information and/or the chip data information written by the multifunctional writer to the imaging box chip. The imaging box chip processing device is suitable for processing schemes such as imaging box chip model number determination, writing and resetting; the processing process is convenient. The imaging box chip processing device is accurate and helpful for enhancing the experience of a user and reducing the extra economic losses and cost burden of the user due to time waste.
Owner:GUANGZHOU ZHONO ELECTRONICS TECH CO LTD

Under-gate technology CMOS (complementary metal oxide semiconductor) device for inhibiting drain induction barrier lower effect and preparation method thereof

The invention provides an under-gate technology CMOS (complementary metal oxide semiconductor) device for inhibiting drain induction barrier reduction effect and a preparation method thereof. The CMOS device comprises an N-type MOS (metal oxide semiconductor) transistor and a P-type MOS (metal oxide semiconductor) transistor, wherein gate grooves of N-type MOS transistor gate and a P-type MOS transistor gate comprise a metal oxide dielectric material layer respectively; ions with different work functions are injected to the metal oxide dielectric material layer, so that the work functions of the N-type MOS transistor gate close to a drain end or two ends of a drain and a source are increased, and the work functions of the P-type MOS transistor gate close to the drain end or close to two ends of the drain and the source are decreased, thus the drain induction barrier lower effect of the CMOS device is inhibited. According to the invention, leakage current of a PN junction at the drain end can not be caused while changing the working functions of the drain end of the CMOS device or the working functions close to two ends of the drain or source so as to inhibit DIBL (drain induction barrier lower) effect effectively, thus the performances of a semiconductor chip are improved effectively; and the method has simple process flow, low implementation cost and no additional cost burden.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP

CMOS (Complementary Metal-Oxide-Semiconductor Transistor) for inhibiting drain induced barrier lowering effect and manufacturing method of CMOS

The invention provides a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) for inhibiting a drain induced barrier lowering effect and a manufacturing method of the CMOS. The CMOS comprises an N-type MOS (Metal-Oxide-Semiconductor) transistor and a P-type MOS transistor, wherein a gate of the N-type MOS transistor and a gate of the P-type MOS transistor respectively comprise a high dielectric layer, a metal oxide dielectric material layer and polysilicon or a metal layer; and ions with different work functions are implanted in the metal oxide dielectric material layer and the polysilicon or the metal layer, so that a work function of the gate of the N-type MOS transistor, which is close to the drain electrode end, is increased, a work function of the gate of the P-type MOS transistor, which is close to the drain electrode end, is reduced and further the drain induced barrier lowering effect of the CMOS is inhibited. While the DIBL (Drain Induced Barrier Lowering) effect is effectively inhibited by changing the work function of the gate of the CMOS, which is close to the drain electrode end, extra increase of drain end PN (Peripheral Node) leakage current can be avoided and the performance of a semiconductor chip is effectively improved; in addition, the manufacturing method has the advantages of simple process flow, low implementation cost and avoidance of extra cost burden.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP
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