CMOS (Complementary Metal-Oxide-Semiconductor Transistor) for inhibiting drain induced barrier lowering effect and manufacturing method of CMOS

Abstract

The invention provides a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) for inhibiting a drain induced barrier lowering effect and a manufacturing method of the CMOS. The CMOS comprises an N-type MOS (Metal-Oxide-Semiconductor) transistor and a P-type MOS transistor, wherein a gate of the N-type MOS transistor and a gate of the P-type MOS transistor respectively comprise a high dielectric layer, a metal oxide dielectric material layer and polysilicon or a metal layer; and ions with different work functions are implanted in the metal oxide dielectric material layer and the polysilicon or the metal layer, so that a work function of the gate of the N-type MOS transistor, which is close to the drain electrode end, is increased, a work function of the gate of the P-type MOS transistor, which is close to the drain electrode end, is reduced and further the drain induced barrier lowering effect of the CMOS is inhibited. While the DIBL (Drain Induced Barrier Lowering) effect is effectively inhibited by changing the work function of the gate of the CMOS, which is close to the drain electrode end, extra increase of drain end PN (Peripheral Node) leakage current can be avoided and the performance of a semiconductor chip is effectively improved; in addition, the manufacturing method has the advantages of simple process flow, low implementation cost and avoidance of extra cost burden.

Description

technical field [0001] The invention relates to a method for manufacturing an integrated circuit, in particular to a CMOS device that suppresses the effect of reducing the drain induction potential barrier. Background technique [0002] Drain induction barrier lower (DIBL) effect is an undesirable phenomenon that occurs in small-sized field effect transistors (FETs) in the semiconductor manufacturing process, that is, when the channel length is reduced, the drain region source The interval voltage (Vds) increases, so that when the depletion layer of the drain junction and the source junction is close, the electric force line in the channel can cross from the drain region to the source region, and cause the barrier height of the source terminal to decrease, so that the source region is injected into the channel The number of electrons increases, resulting in an increase in the drain current. And when the channel length is shorter, the DIBL effect is more serious. [0003] T...

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Problems solved by technology

[0006] The invention provides a method for suppressing the induced barrier lowering effect of the semiconductor drain, aiming at the existing deficiencies in suppressing the DIBL effect, by implanting ions into the semiconductor gate close to the drain to locally change the work function of the gate, thereby achieving suppression The purpose of the DIBL effect will not cause an additional increase in the leakage current of the PN junction at the drain

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