Under-gate technology CMOS (complementary metal oxide semiconductor) device for inhibiting drain induction barrier lower effect and preparation method thereof

Abstract

The invention provides an under-gate technology CMOS (complementary metal oxide semiconductor) device for inhibiting drain induction barrier reduction effect and a preparation method thereof. The CMOS device comprises an N-type MOS (metal oxide semiconductor) transistor and a P-type MOS (metal oxide semiconductor) transistor, wherein gate grooves of N-type MOS transistor gate and a P-type MOS transistor gate comprise a metal oxide dielectric material layer respectively; ions with different work functions are injected to the metal oxide dielectric material layer, so that the work functions of the N-type MOS transistor gate close to a drain end or two ends of a drain and a source are increased, and the work functions of the P-type MOS transistor gate close to the drain end or close to two ends of the drain and the source are decreased, thus the drain induction barrier lower effect of the CMOS device is inhibited. According to the invention, leakage current of a PN junction at the drain end can not be caused while changing the working functions of the drain end of the CMOS device or the working functions close to two ends of the drain or source so as to inhibit DIBL (drain induction barrier lower) effect effectively, thus the performances of a semiconductor chip are improved effectively; and the method has simple process flow, low implementation cost and no additional cost burden.

Description

technical field [0001] The invention relates to an integrated circuit manufacturing method, in particular to a gate-last process CMOS device which suppresses the effect of lowering the drain induction potential barrier. Background technique [0002] Drain induction barrier lower (DIBL) effect is an undesirable phenomenon that occurs in small-sized field effect transistors (FETs) in the semiconductor manufacturing process, that is, when the channel length is reduced, the drain region source The interval voltage (Vds) increases, so that when the depletion layer of the drain junction and the source junction is close, the electric force line in the channel can cross from the drain region to the source region, and cause the barrier height of the source terminal to decrease, so that the source region is injected into the channel The number of carriers increases, resulting in an increase in drain current. And when the channel length is shorter, the DIBL effect is more serious. ...

AI Technical Summary

Problems solved by technology

[0007] The invention provides a gate-last process CMOS device that suppresses the effect of drain-induced barrier lowering. It aims at the existing deficiency of suppressing the DIBL effect, and locally changes the work of the gate by implanting ions into the semiconductor gate close to the drain. Function, so as to achieve the purpose of suppressing the DIBL effect, and will not cause an additional increase in the leakage current of the drain PN junction

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