Method for forming fins and fin field effect transistors

Abstract

A method for forming a fin portion and a fin field effect transistor is provided. The method for forming the fin portion comprises: providing a semiconductor substrate, forming a hard mask layer on the semiconductor substrate, wherein the hard mask layer is provided with a plurality of adjacent openings; etching the semiconductor substrate along the openings and thus a plurality of first grooves are formed, wherein the positions of the first grooves are corresponding to the positions of the openings, and a first sub-fin portion is formed between the two adjacent first grooves; filling isolation materials fully in the first grooves and the corresponding openings, and thus isolation structures are formed; removing the hard mask layer, and thus a plurality of second grooves are formed; filling isolation materials in the second grooves, and thus second sub-fin portions are formed; back etching the isolation structures and thus the side walls of the second sub-fin portions are exposed; and performing planarization treatment on the side walls of the second sub-fin portions. After planarization treatment, the shapes of the edges and the side wall surfaces of the second sub-fin portions exhibit better uniformity; and after a gate structure which stretches across the second sub-fin portions is formed, the stability of a threshold voltage of the fin field effect transistor is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming fins and fin field effect transistors. Background technique [0002] With the continuous development of semiconductor process technology, as the process node gradually decreases, gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (FinFET) as a conventional device substitution has received extensive attention. [0003] figure 1 A schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art is shown. like figure 1 As shown, it includes: a semiconductor sub...

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Problems solved by technology

[0005] The uniformity of the topography of the edges and sidewalls of the fins 14 formed in the prior art is poor, and the differences in the topography uniformity of the edges and sidewalls of the fins 14 will cause the threshold voltage of the fin field effect transistor to shift. , affecting the stability of the FinFET

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