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SPI interface and method for serial communication via an SPI interface

A technology of SPI interface and serial clock, which is applied in the directions of multiplexing communication, signal generation/distribution, transmission system, etc., and can solve the problems that the correct timing cannot be guaranteed, and timing violations cannot be completely removed.

Active Publication Date: 2014-01-29
INFINEON TECH AG
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

It depends on the implementation (using analog filters, etc.), but in the worst case all flip-flops of the interface become metastable (i.e. flip-flops are in an unstable state between "low" and "high" states medium, and after an indeterminate duration will become a steady state "low" or "high") and can cause random behavior with severe consequences
[0009] However, in noisy environments, correct timing cannot be guaranteed due to the unpredictability of random noise events
In conventional SPI devices, analog filters are often used to suppress glitches on the clock signal, however the use of analog filters cannot completely remove timing violations due to noise-induced events: for example, an analog filter can pass too small a clock pulse , which causes the SPI flip-flop to become metastable

Method used

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  • SPI interface and method for serial communication via an SPI interface
  • SPI interface and method for serial communication via an SPI interface

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Embodiment Construction

[0017] In the following detailed description, referring to the accompanying drawings, the accompanying drawings form a part of the following detailed description, and are shown by showing specific embodiments in which the present invention can be implemented. It should be understood that other embodiments may be utilized, and structural or other changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not intended to be limiting, and the scope of the present invention is defined by the appended claims.

[0018] figure 1 Illustratively shows a simplified schematic diagram of an SPI interface according to an embodiment of the present invention.

[0019] figure 1 The SPI interface shown includes a serial data input (SDI) signal input terminal 11a, a chip select (CS) signal input terminal 11b, a serial clock (SCLK) signal input terminal 11c, and a serial data output (SDO) signal output terminal 11d , The internal c...

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Abstract

The invention relates to serial communication with peripheral devices using the Serial Peripheral Interface (SPI) protocol, in particular to an SPI interface for a noisy environment and a method for serial communication via an SPI interface in a noisy environment. In accordance with an aspect of the invention, there is provided an SPI interface comprising a plurality of synchronizers configured to receive a plurality of SPI signals and an internal clock signal and synchronize the received SPI signals using the internal clock signal and an SPI protocol handler configured to receive the synchronized SPI signals and the internal clock signal and detect and evaluate signal transitions of at least one of the synchronized SPI signals according to an SPI protocol.

Description

Technical field [0001] The present invention relates to serial communication with peripheral devices using a serial peripheral interface (SPI) protocol, and in particular, to an SPI interface for a noisy environment and a serial communication method via the SPI interface in a noisy environment. Background technique [0002] The Serial Peripheral Interface (SPI) protocol is a protocol widely used for data transmission between integrated circuits (ICs), especially the host processor (also known as SPI host) and one or more peripheral devices (also known as SPI Slave). The SPI protocol specifies four signals: [0003] CS: Chip selection [0004] SCLK: shift clock or serial clock [0005] SDI: shift data input or serial data input [0006] SDO: shift data output or serial data output [0007] However, it should be understood that alternative naming conventions are also widely used. [0008] The SPI protocol is a synchronous protocol, which requires a defined timing for correct operation. ...

Claims

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Application Information

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IPC IPC(8): G06F13/42
CPCG06F13/4291H04J3/0685H03K5/1252H04L7/0331Y02D10/00G06F13/42G06F1/12
Inventor 托马索·巴奇加卢波
Owner INFINEON TECH AG
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