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Flash memory device and operating method thereof

A technology for flashing memory and reading instructions, applied in the field of flash memory devices and their operations

Active Publication Date: 2014-01-29
WINBOND ELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

Multiple registers to store logic data

Method used

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  • Flash memory device and operating method thereof
  • Flash memory device and operating method thereof
  • Flash memory device and operating method thereof

Examples

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Embodiment Construction

[0070] Flash memory can be widely used in digital electronic devices and systems. However, devices and systems with high performance generally require flash memory to operate at a higher frequency. For example, in the case of a memory read operation, although using a dummy clock after the instruction may allow higher frequency operations, a bottleneck may still occur in the speed of the logical read operation. This problem is caused by excessive delays in instruction decoding and logic circuits, data register circuits, and interconnection internal signal lines.

[0071] For example, the signal JEDEC read command (9Fh), the first status register read command (signal RDSR105h ), and the second status register read command (signal RDSR235h ) are examples of logical read commands. The signal JEDEC read command outputs the manufacturer and device identity bytes from the device to determine the identity of the device. The read commands of the signals RDSR1 and RDSR2 respectively o...

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Abstract

The invention relates to a flash memory device and an operating method thereof. A logic read operation opportunity in the flash memory device can be improved by a bonding pad serial output circuit, the bonding pad serial output circuit receives a pre-decoding command signal and a pre-fetching logic signal before a final command clock pulse, and the pre-decoding command signal and the pre-reading logic signal execute rapid analysis on a command in the bonding pad serial output circuit in a final pulse of a command input sequence. In another embodiment, pre-decoding of a first command and data pre-fetching can be executed in a fourth clock pulse input by the command, and pre-decoding of a second command can be executed in a seventh clock pulse input by the command. Two serial protocol interfaces and quaternary peripheral interfaces of binary and quaternary input / output serial peripheral interfaces can support the flash memory device.

Description

technical field [0001] The present invention relates to a flash memory device and its operating method, and more particularly to a device and method for reading logical data on the flash memory. Background technique [0002] Single-bit serial and multi-bit serial flash memory have become common due to the low number of pins and simple interfaces. The simplest interface is a serial peripheral interface (Serial Peripheral Interface, SPI). The one-bit SPI communication protocol involves the user sending 8-bit commands, address bytes, and optionally dummy bytes to the SPI flash device, and the SPI flash device will send back data to the user in response. A single 8-bit command can identify a read, erase / program, or another appropriate operation. For high-performance system applications that require fast read performance, such as dual serial peripheral interface (SPI-Dual), quad serial peripheral interface (SPI-Quad), and quad peripheral interface (Quad Peripheral Interface, Q...

Claims

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Application Information

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IPC IPC(8): G11C16/10G11C16/26
Inventor 陈毓明苏腾厉志刚
Owner WINBOND ELECTRONICS CORP
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