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Shared memory based data access method and device

A shared memory and data access technology, applied in the field of data processing, can solve the problems of high usage frequency, system crash, and high real-time requirements, and achieve the effects of improving stability, improving real-time performance, and improving access speed.

Inactive Publication Date: 2014-02-05
AUTEL INTELLIGENT TECHNOLOGY CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the existing technology, the main method for data interaction between processors is the serial communication module (UART, USB, etc.), this communication mode can basically meet the requirements of most applications, but in applications with large data volume and high time requirements However, shared memory technology is one of the communication methods for data interaction between multi-core processors. It is designed to enable multi-cores to cooperate to complete a specific function, and access data quickly and in real time. However, the occurrence of access conflicts between multi-core shared memory data access is a difficult problem for most engineers in software application development. The existing shared memory data interaction technology does not have a unified method, and software engineers are designing such applications. When accessing data, there are often data access errors, memory access out of bounds, and serious system crashes. The usual implementation method is: A and B processors apply for a shared memory as a data exchange buffer, and A processor uses memory in this memory area. Put new data and set flag C, processor B detects whether there is data in this memory area, and tries to take away the data and modify flag C, but at this time, if processor A receives new data and needs to put it in this memory area, When the B processor has not modified the flag or taken the data, it caused the conflict of reading and writing of the data. The real-time requirements are relatively high. The B processor should have received the correct two packets of data. In fact, it only takes A packet of wrong data has arrived. In the existing method, the processor needs to constantly detect whether new data is received, and the frequency of use is too high

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  • Shared memory based data access method and device

Examples

Experimental program
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Embodiment 1

[0052] figure 1 It is a flow chart of the shared memory-based data access method provided by Embodiment 1 of the present invention.

[0053] A data access method based on shared memory, comprising:

[0054] The first processor applies for a first data buffer from a preset shared memory area, so that the first processor sends data to the second processor;

[0055] The first processor saves the data to be sent in the first data buffer, and sends an interrupt instruction to the second processor;

[0056] After the second processor receives the interrupt instruction, it judges whether there is data to be read in the first data buffer, if so, reads the data to be read, if not, does not perform read operation.

[0057] Such as figure 2 As shown, in this embodiment, the shared memory area further includes a second data buffer, and the second data buffer is used to store data sent by the second processor to the first processor.

[0058] In this embodiment, if the second processor ...

Embodiment 2

[0077] Such as Figure 5 As shown, it is a schematic structural diagram of a data access device based on shared memory provided by Embodiment 2 of the present invention.

[0078] A data access device based on shared memory, comprising:

[0079] The application unit is used for the first processor to apply for the first data buffer to the preset shared memory area, so that the first processor sends data to the second processor;

[0080] a storage unit, configured for the first processor to store the data to be sent in the first data buffer, and send an interrupt instruction to the second processor;

[0081] The reading unit is used for the second processor to judge whether there is data to be read in the first data buffer after receiving the interrupt instruction, and if so, read the data to be read.

[0082] In this embodiment, the first data buffer includes a read data pointer area, a write data pointer area, a data initial storage area, a reserved area, a valid data area, ...

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Abstract

The invention relates to the field of data processing, in particular to a shared memory based data access method and device. The method comprises steps as follows: a first processor applies a first data buffer area in a preset shared memory area; the first processor preserves data required to be sent in the first data buffer area and sends an interrupt instruction to a second processor; after the second processor receives the interrupt instruction, whether data required to be read exist in the first data buffer area is judged; and the data required to be read are read if the data exist. According to the method, the shared memory area is divided, so that one processor writes data and the other processor reads data in each subarea, the two processors are prevented from writing and reading data in the same area, the conflict problem of the two processors is solved, the data access speed is effectively increased, data notification is performed according to the intercept instruction, and the real-time performance of data access is improved.

Description

technical field [0001] The invention relates to the field of data processing, in particular to a shared memory-based data access method and device. Background technique [0002] In the existing technology, the main method for data interaction between processors is the serial communication module (UART, USB, etc.), this communication mode can basically meet the requirements of most applications, but in applications with large data volume and high time requirements However, shared memory technology is one of the communication methods for data interaction between multi-core processors. It is designed to enable multi-cores to cooperate to complete a specific function, and access data quickly and in real time. However, the occurrence of access conflicts between multi-core shared memory data access is a difficult problem for most engineers in software application development. The existing shared memory data interaction technology does not have a unified method, and software engine...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/455
Inventor 李红京余世均
Owner AUTEL INTELLIGENT TECHNOLOGY CORP LTD