Triggering vibration real-time correction circuit and method in random sampling process

Abstract

The invention provides a triggering vibration real-time correction circuit and method in a random sampling process. A triggering signal and sampling clocks are set to be connected with a triggering control unit in a programmable logic unit, and then set to be connected with a precise inserted-in unit in the programmable logic unit after four ways of sequence signals are generated, the time interval t1 between the rising edge of the triggering signal and the rising edge of the next first sampling clock or the time interval t2 of one sampling clock or the time interval t3 between two sampling cycles is set to a widening circuit or a comparator, and then set to be connected with a precise inserted-in counter in the programmable logic unit, and generated counting values are input to a digital signal processor, the t1 is a precise inserted-in time interval needing to be measured, and the t2 and the t3 are used for correcting the inserted-in time. Through the technical scheme, a digital precise inserted-in time discrimination circuit is achieved inside an FPGA, and triggering vibration is eliminated through the optimization design of a double-slope expander circuit and the correction technology of the inserted-in time.

Description

technical field [0001] The invention belongs to the technical field of pulse power measurement, and in particular relates to a trigger jitter real-time correction circuit method in a random sampling process. Background technique [0002] In pulse power measurement, if real-time sampling is used, a sufficiently high sampling rate is required, and to increase the sampling rate, a high-speed A / D converter must be used, but high-speed A / D and sample memory are expensive. In most cases, the measurement signal is a periodic signal, so in order to obtain a high repetitive signal measurement bandwidth at a lower sampling rate, the system uses random sampling for data acquisition. [0003] At present, for the measurement of the precise interpolation time of the trigger signal and the sampling clock, it is mainly through a series of D flip-flops to generate the precise interpolation time, and after being widened by a double-slope widening circuit, it is shaped by a comparator and coun...

AI Technical Summary

Problems solved by technology

[0004] The disadvantages of adopting the prior art are: 1, the interpolation time discrimination circuit uses a plurality of ECL level D flip-flops, the cost is high, the power consumption is large, causes serious heating, and increases the circuit board volume; 2, double slope widening circuit The nonlinear error in the expansion factor K is unstable, which affects the accuracy of the interpolation time and cannot completely eliminate the trigger jitter.

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