A Synchronization Method for Dual-channel Digital-to-Analog Converters

Abstract

Discloses is a dual-channel digital analog converter synchronization method. A dual-channel digital analog converter comprises a first digital analog converter and a second digital analog converter. The method comprises the following steps: outputting a first reference clock to an FPGA by the first digital analog converter, and outputting a second reference clock to the FPGA by the second digital analog converter; performing phase demodulation on the second reference clock through the FPGA by utilizing the first reference clock; obtaining the phase difference of the two reference clocks; outputting the first reference clock directly as a first data clock by the FPGA; adjusting the second reference clock according to the phase difference of the two reference clocks to obtain a second data clock; accordingly synchronizing the first data clock with the second data clock; and outputting data to the first digital analog converter by the FPGA according to the first data clock, and outputting data to the second digital analog converter by the FPGA according to the second data clock. By using the method provided by the invention, two 1.2GSPS digital analog converters can be enabled to output simulation signals with the same phase.

Description

technical field [0001] The present invention relates to a dual-channel DAC synchronization method. Background technique [0002] For some simulations, two RF output channels are required, and their amplitude, phase, Doppler and distance are required to be precisely controlled by software, in order to achieve the simulation results, especially the precise control of the phase. Therefore, at the beginning of the simulation, the initial phase difference of the two channels should be kept fixed, that is to say, the initial phase of each DAC output signal should be kept the same. like figure 1 Shown is the hardware schematic diagram of the traditional two-channel simulation, and the initial phase difference of the output of the two channels is required to be fixed; figure 1 Two low-speed DACs + single-chip FPGA are used for dual-channel simulation, which can achieve synchronization, but the bandwidth is small, which cannot meet the needs of radar simulation in modern systems. ...

AI Technical Summary

Problems solved by technology

Since no phase calibration is performed, the single-point frequency signals output by DA1 and DA2 are not synchronized at this time

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