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semiconductor storage device

A storage device and semiconductor technology, applied in information storage, static storage, digital storage information, etc., can solve problems such as reducing the power supply voltage of storage cells, and achieve the effect of reliable storage and preservation

Active Publication Date: 2017-02-15
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] According to a prior art, in order to reduce the leakage current of the memory cell, the power supply voltage of the memory cell is lowered for each row

Method used

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Experimental program
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Effect test

no. 1 approach

[0034] figure 1 It is a configuration diagram of the semiconductor memory device according to the first embodiment of the present invention. figure 1 The shown semiconductor storage device includes: a memory cell 10 composed of access transistors A1-2, drive transistors D1-D2, and load transistors L1-2 to have two storage nodes N1-2, a bit line precharge circuit 15, A memory cell power supply circuit 20 composed of P-type MOS transistors MP1-2, a leakage current compensation circuit 25, a power supply voltage detection circuit 30, an inverter circuit INV1, and a NAND circuit NAND1. WL0-x indicates word line, BL0-1 and / BL0-1 indicate bit line, PCG indicates precharge control signal, VDDM0-1 indicates memory cell power supply, AD0-1 indicates column address signal, WEN indicates write control signal, VDD Indicates a power source (first power source). X is an integer greater than 1, figure 1 A case where there are a plurality of memory cells 10 connected to a plurality of wor...

no. 2 approach

[0139] Figure 9 It is a block diagram of the semiconductor memory device which concerns on the 2nd Embodiment of this invention. Figure 9 The semiconductor memory device shown is relative to that in the first embodiment figure 1 In the illustrated configuration, only the configuration of the MOS transistors constituting the memory cell power supply circuit 21 is different. Specifically, an N-type MOS transistor MN2 is added between the P-type MOS transistor MP2 and the ground power supply. The gate terminal of the P-type MOS transistor MP2 is connected to the drain terminal of the N-type MOS transistor MN2, and the same signal as the signal input to the gate terminal of the P-type MOS transistor MP1 is input to the gate of the N-type MOS transistor MN2. extreme extreme.

[0140] The write control signal WEN is at the L level (inactive state) except when the write operation is performed. Therefore, regardless of the state of the column address signals AD0 and AD1, the NAN...

no. 3 approach

[0147] Figure 10 It is a configuration diagram of a semiconductor memory device according to a third embodiment of the present invention. Figure 10 The semiconductor memory device shown is relative to the first embodiment figure 1 In terms of the structure in the memory cell, only the control of the memory cell power supply circuit 20 is different. Specifically, the difference is that the signal line of the write control signal WEN is connected to the gate terminals of the P-type MOS transistors MP1 of all the memory cell power supply circuits 20 .

[0148] The write control signal WEN is at the L level (inactive state) except when the write operation is performed. Therefore, the NAND circuit NAND1 outputs the H level regardless of the state of the column address signals AD0 and AD1. Therefore, since the P-type MOS transistor MP1 constituting the memory cell power supply circuit 20 is turned on and the P-type MOS transistor MP2 is turned off, all the memory cell power sup...

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Abstract

The storage unit power supply circuit (20) on each column is formed by the first P-type MOS transistor (MP1) and the second P-type MOS transistor (MP2) connected in series between the first power supply and the second power supply, and the storage unit power supply outputs the first The junction voltage of a P-type MOS transistor (MP1) and a second P-type MOS transistor (MP2). The control signal generated based on the column selection signal and the write control signal is input to the gate terminal of the first P-type MOS transistor (MP1), and the inverted signal of the signal input to the gate terminal of the first P-type MOS transistor (MP1) is input to the second P-type MOS transistor (MP1). Gate terminal of two P-type MOS transistors (MP2).

Description

technical field [0001] The present invention relates to a control technology for controlling the power supply voltage of a storage unit in a semiconductor storage device such as a static random access memory (SRAM). Background technique [0002] In recent years, along with miniaturization of semiconductor manufacturing processes, variations in characteristics of transistors constituting semiconductor memory devices have been increasing. Furthermore, the lowering of the power supply voltage of semiconductor memory devices has been further advanced. [0003] According to a certain prior art, in order to reduce the leakage current of the memory cells, the power supply voltage of the memory cells is lowered for each row. Specifically, the high power supply voltage of the memory cell on the non-selected row is controlled to a voltage value lower than the VDD level (see Patent Document 1). [0004] According to yet another prior art, in order to ensure a sufficiently large stati...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413
CPCG11C11/413G11C11/419G11C11/417
Inventor 山上由展小岛诚里见胜治
Owner SOCIONEXT INC
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