Floating gate electricity erasable read-only memory and manufacturing method thereof

Abstract

The invention discloses a floating gate electricity erasable read-only memory. Source and drain regions are of buried layer structure, and are formed before a tunneling oxidation layer. Before a thermal oxidation process is used to form the tunneling oxidation layer, the thickness of a thermal oxidation layer which is located above source and drain regions is greater than the thickness of a thermal oxidation layer which is located above a channel region. Coupling capacitance of source and drain regions and a floating gate can be reduced. The coupling coefficient of the memory can be improved. The operation voltage of the device is reduced. According to the memory provided by the invention, doped regions of source and drain regions of the same column can be respectively connected together, and lead out and form a source line end and a bit line end of the column through a contact hole; forming a contact hole for leading out in each source region and each drain region is not needed, thus the area of a memory unit can be greatly reduced, and the device cost can be greatly reduced; and the floating gate electricity erasable read-only memory of lower cost can be manufactured. The invention further discloses a manufacturing method of the floating gate electricity erasable read-only memory.

Description

technical field [0001] The invention relates to the manufacturing field of semiconductor integrated circuits, in particular to a floating gate electrically erasable read-only memory; the invention also relates to a manufacturing method of the floating gate electrically erasable read-only memory. Background technique [0002] Non-volatile memory (NVM) technology has been developed so far, mainly including floating gate technology, split gate technology and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon oxide oxynitride silicon) technology. In order to obtain higher performance and larger storage capacity, embedded non-volatile memory (NVM) hopes that the area of ​​the storage unit should be as small as possible. Compared with other technologies, floating gate NVM has the advantage of higher data retention capacity, so floating gate (floating gate) technology has always been the mainstream technology of electrically erasable read-only memory (EEPROM), which has the chara...

AI Technical Summary

Problems solved by technology

One of the characteristics of EEPROM is that it has a high operating voltage and the thickness of its tunnel oxide layer cannot be reduced, which leads to a relatively large area of ​​the cell structure of the memory, so the production cost of its cell structure has always been relatively high

At the same time, the reduction of the size of the floating gate itself will cause the reduction of the dielectric area between the floating gate and the control gate, that is, the reduction of the coupling capacitance, which will reduce the voltage coupling efficiency and reduce the performance of the device, so the size of the EEPROM is reduced. face difficulties

Images