A Low-power Phase Detector Used in All-Digital Phase-Locked Loop

Abstract

The invention belongs to the microelectronic field, and relates to a phase discriminator used for a full digital phase-locked loop; under a prerequisite of ensuring the correct function of the phase discriminator, the power consumption of the phase discriminator can be reduced. A conventional phase discriminator is improved; the output of an accumulated counter is the result of accumulating output code values of a conventional counter in various reference clock periods instead of being the output code value in one single clock period, so the accumulated counter can be directly driven by a DOC output signal; an operation sequence of the output of a time-digital converter in the digital phase discriminator is exchanged, so operation steps of the whole phase discriminator is reduced, thereby reducing power consumption of the phase discriminator structure, and the circuit structure is simpler and easy to realize. The phase discriminator of the invention is suitable for circuit design of the full digital phase-locked loop, and has very important practical value.

Description

technical field [0001] The invention belongs to the field of microelectronics and relates to a phase detector used for an all-digital phase-locked loop; the phase detector can reduce the power consumption of the phase detector under the premise of ensuring the correct function of the phase detector. Background technique [0002] The phase-locked loop structure (PLL) is more and more widely used in the field of wireless communication and digital circuit clock recovery. The traditional PLL circuit is made of fully customized (analog / RF circuit), and the performance of the circuit is affected by PVT (process, power supply voltage, temperature) is relatively large; on the other hand, tens of nanometers of CMOS technology has brought great benefits to digital circuits, but it has little benefit to analog / RF circuits, because the analog / RF circuits Passive parts (capacitors, inductors, etc.) have not been scaled down with the process, and the development of the process has reduced...

AI Technical Summary

Problems solved by technology

[0003] But the operation in the digital phase detector of the described ADPLL is the addition and subtraction of tens of bit numbers, so there is a relatively high power consumption; Digital Phase Detector Architecture for Power Dissipation

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