Fast Delay-Locked Loop with Delay Chain Control Code Adaptation

Abstract

The invention discloses a time-delay chain control code self-adaptive rapid delay lock loop comprising a digital control time-delay chain which is used for generating four clock signals with mutual phase differences of 90 degrees, a phase discriminator used for outputting advanced signals or lagging signals of time delay difference indication signals, a coarse adjustment time-to-digital converter used for outputting coarse adjustment time-delay chain control codes; a coarse adjustment bidirectional shift register chain used for generating and outputting the coarse adjustment time-delay chain control codes, a fine adjustment time-to-digital converter used for generating and outputting fine adjustment time-delay chain control codes, and a fine adjustment bidirectional shift register chain used for generating and outputting the fine adjustment time-delay chain control codes. If the fine adjustment time-delay chain control codes can not satisfy time-delay adjusting, starting control signals are generated to control the coarse adjustment bidirectional shift register chain to carry out readjusting of the coarse adjustment time-delay chain. If the fine adjustment time-delay chain control codes satisfy the time-delay adjusting, the starting control signals are switched off through the fine adjustment time-to-digital converter and the fine adjustment bidirectional shift register chain.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, relates to a delay phase-locked loop technology, and is a fast delay-locked loop adaptive to a delay chain control code, and the fastest locking time is 8 clock cycles. Background technique [0002] With the continuous development of integrated circuit technology, the integration level is getting higher and higher, the chip area is getting larger and larger, and the minimum line width is getting narrower and narrower, resulting in longer and longer path delays. On the one hand, the system has higher and higher requirements on the clock; on the other hand, the problem of asynchronous clock edges of various parts of the system is becoming more and more serious. In order to solve the problem of clock asynchrony, the system needs a delay-locked loop to generate the required phase clock. [0003] The basic idea of ​​a delay-locked loop is to delay the output clock so that it can be perfec...

AI Technical Summary

Problems solved by technology

In addition, since the delay-locked loop does not have a coarse-tuning control code adjustment circuit, in some non-ideal situations, that is, when the feedback clock lags behind the reference clock, the delay-locked loop will not be able to achieve system locking

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