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High-speed serial-parallel conversion circuit based on FPGA

A conversion circuit, high-speed technology, applied in parallel/serial conversion, code conversion, electrical components, etc., can solve the problems of complex realization, fixed structure, limited application scope, etc., and achieve the effect of cost reduction

Inactive Publication Date: 2014-03-26
NANJING UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually the serial-to-parallel conversion chips used in various fields, such as 74hc595, 74hc166, etc., are limited in their application range due to their fixed structure and single variety.
[0003] In the prior art, if the serial-to-parallel conversion circuit is built independently, there are often disadvantages such as inflexible design, high cost, and complicated implementation.

Method used

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  • High-speed serial-parallel conversion circuit based on FPGA
  • High-speed serial-parallel conversion circuit based on FPGA
  • High-speed serial-parallel conversion circuit based on FPGA

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Embodiment Construction

[0017] The FPGA-based high-speed serial-to-parallel conversion circuit of the present invention can collect and output multiple bits in parallel after passing the high-speed serial digital signal through the FPGA-based multi-stage delay tap device and multi-stage receiving memory under the low-speed clock. Digital signal.

[0018] The present invention is based on the high-speed serial-to-parallel conversion circuit of FPGA, and its realization circuit is made up of multi-stage delay tap device and multi-stage receiving memory two parts, and realization method is as follows:

[0019] 1. The high-speed digital signal enters the multi-level delay tap to output the multi-level delayed signal;

[0020] Second, the delay signals at all levels correspond to the D flip-flops input to the multi-level receiving memory. When the next clock arrives, the current input D flip-flop signal is stored and output, thereby realizing the serial to parallel conversion of signals within a single cl...

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Abstract

The invention discloses a high-speed serial-parallel conversion circuit based on an FPGA. Under a low-speed clock, high-speed serial digital signals pass through a multi-level delaying tapping device and a multi-level receiving storage based on the FPGA and then are collected in one cycle, and multi-bit digital signals are output in parallel. The high-speed serial-parallel conversion circuit is achieved through the FPGA, serial-parallel conversion processing on the high-speed digital signals can be completed through a low-speed digital circuit, system cost is lowered, circuit designing is simplified, and high cost performance is achieved.

Description

technical field [0001] The invention belongs to a signal serial-to-parallel conversion circuit, in particular to an FPGA-based high-speed digital signal serial-to-parallel conversion circuit. Background technique [0002] Digital signal serial-to-parallel conversion circuits are an important part of electronic information and communication applications, and are widely used in many fields such as national defense, aerospace, and remote sensing. Usually, the serial-to-parallel conversion chips used in various fields, such as 74hc595, 74hc166, etc., have a fixed structure and a relatively single variety, which limits their application range. [0003] In the prior art, if the serial-to-parallel conversion circuit is built independently, there are often disadvantages such as inflexible design, high cost, and complicated implementation. Contents of the invention [0004] The purpose of the present invention is to propose a method for serial-to-parallel conversion of high-speed ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M9/00
Inventor 李洪涛马义耕顾陈朱晓华陈诚王超宇
Owner NANJING UNIV OF SCI & TECH
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