Gearbox circuit for reducing data bit width under condition of not changing Baud rate of data transmission and working method

Abstract

The invention relates to a gearbox circuit for reducing the data bit width under the condition of not changing the Baud rate of data transmission and a working method. The gearbox circuit comprises a data bit width switching circuit, a counter generation circuit and a flag bit generation circuit. The output end of the counter generation circuit is connected with the data bit width switching circuit and the flag bit generation circuit respectively. According to a gearbox, a synchronous clock of input data of the gearbox can be utilized as the clock used for output data, an additional input clock is not needed, as a result, the design of a clock circuit is simplified, additional expenses for circuit design of an overall system are reduced, and design reliability is improved. The gearbox circuit is particularly suitable for circuit interior design; when data bit widths between modules or all IPs are not matched, the data bit widths between the modules are adjusted under the condition of not changing the Baud rate of data transmission, so that data bit width matching between all the internal modules is realized.

Description

technical field [0001] The invention relates to a gearbox circuit and a working method, and is particularly suitable for a gearbox circuit and a working method for reducing the data bit width without changing the data transmission baud rate. [0002] Background technique [0003] With the development of SOC to a high degree of integration, the scale of SOC circuits is getting larger and larger, and circuits with tens of millions of gates can be found everywhere. Various modules and IPs are integrated in SOC circuits, such as high-speed port transceivers, SRAM, DSP. The number of waiting is also increasing. This brings a problem. The modules or IPs developed by different manufacturers often have different data bit widths. For example, in the physical layer standard of 10G-WIS of 10G Ethernet, the data sent from the upper layer protocol needs to be encoded by 64B / 66B first, and then enter the PCS of the 10G-WIS standard for data processing. However, the data bit width defin...

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Problems solved by technology

[0004] If directly based on the principle that the data output and input data rates on both sides of the gearbox are equal, two frequency clocks are used to directly convert the data bit width from more to less, without any control on the clocks or data on both sides , because the clock frequency of the gearbox data output is greater than the clock frequency of the gearbox data input, that is, the clock period used for the output data is smaller than the width of the input data, so in the process of data bit width conversion, due to the frequency difference between the two clocks, in In a certain clock cycle, the clock that outputs data will sample the data in the current cycle twice, resulting in duplication of output data and affecting the correctness of data transmission.

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