Parasitic Extraction Method and System in Integrated Circuits with Multiple Pattern Formation Requirements

Abstract

Systems and methods are provided for extracting parasitics in the design of integrated circuits with multiple patterning requirements. The method includes determining a resistive solution and a capacitive solution. The method also includes performing a parasitic extraction of the resistive solution and the capacitive solution to generate an average value of the resistive solution and the capacitive solution. The method also includes forming a source of variation for each captured multi-pattern of resistive and capacitive solutions during parasitic extraction. The method also includes determining a sensitivity of each captured source of variation to a respective vector of parameters. The method also includes determining statistical parasitics by multiplying each of the resistive solution and the capacitive solution by the determined sensitivity to each respective captured source of variation. The method also includes generating statistical parasitics as output in at least one of a vector form and a collapse-reduced vector form.

Description

technical field [0001] The present invention relates to systems and methods for integrated circuit ("IC") fabrication and optimization, and more particularly to methods for extracting parasitics in the design of integrated circuits with multi-patterning requirements. systems and methods. Background technique [0002] An IC is a device (eg, a semiconductor device) or electronic system that includes many electronic components such as transistors, resistors, diodes, and the like. These components are often interconnected to form multiple circuit components such as gates, cells, memory units, arithmetic units, controllers, decoders, and the like. An IC includes multiple wiring layers that interconnect its electronic and circuit components. [0003] Design engineers design ICs by transforming a logical or circuit description of the IC's components into a geometric description called the design layout. An IC design layout typically includes circuit blocks with pins (eg, a geome...

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Problems solved by technology

However, splitting the layers into multiple masks can cause timing variations due to mask misalignment during fabrication

For example, misalignment of layout masks can lead to variations in coupling capacitance between polygons on different masks, which in turn affects both the net's total capacitance and coupling

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