Anti-single event upset and anti-single event transient settable reset scanning structure D trigger
A single-event transient and anti-single-event technology, which is applied in the direction of pulse generation, electrical components, and electric pulse generation, can solve the problems of anti-single-event flipping ability and anti-single-event transient.
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[0045] image 3 It is a schematic diagram of the logic structure of the anti-single-event upset and single-event transient settable and resettable scanning structure D flip-flop of the present invention. The present invention consists of a clock circuit (such as Figure 4 shown), snubber circuits (such as Figure 5 shown), scan control buffer circuit (such as Figure 6 shown), set buffer circuits (such as Figure 7 shown), reset snubber circuit (as Figure 8 shown), the master latch (as Figure 9 shown), slave latches (as Figure 10 shown) and the output buffer circuit (as Figure 11shown) composition. The anti-single-event reversal and anti-single-event transient settable and resettable D flip-flop of the invention has six input terminals and one output terminal. The six input terminals are clock signal input terminal CK, data signal input terminal D, scanning control signal input terminal SE, scanning data input terminal SI, set signal input terminal SN and reset sig...
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