Active discharging mechanism of discrete magnitude port

Abstract

The invention provides an active discharging mechanism of a discrete magnitude port. A grid electrode of a high-voltage nmos transistor is controlled through a logic control circuit, so that high-voltage temporarily-stored charges are rapidly discharged, delay, caused by the temporarily-stored charges, of the discrete magnitude port is avoided, namely, the purpose that discrete magnitude processing signals are rapidly responded through the method that the temporarily-stored charges of the discrete magnitude port are discharged is achieved, the active discharging mechanism is suitable for all systems containing discrete magnitude signals, and therefore the systems containing the discrete magnitude signals can process the discrete magnitude signals through chips with the active discharging function. The active discharging mechanism of the discrete magnitude port is an in-chip circuit, so that periphery devices are not needed, and the cost of a PCB is reduced.

Description

technical field [0001] The invention belongs to the microelectronic circuit design technology, in particular to an active discharge mechanism of a discrete port. Background technique [0002] Discrete quantities generally exist in electromechanical systems, and different parts of the system generate discrete quantity signals of different levels. When the line level is switched, due to the effect of parasitic resistance and capacitance on the board, there is a temporary charge at the port after the level is switched to an open circuit, and the temporary charge causes a large delay between the control signal and the processed TTL signal. Contents of the invention [0003] The purpose of the present invention is to provide an active discharge mechanism of a discrete quantity port to achieve the purpose of accelerating the rapid response of the discrete quantity processing signal. [0004] Concrete technical solution of the present invention is as follows: [0005] The activ...

AI Technical Summary

Problems solved by technology

When the line level is switched, due to the parasitic resistance and capacitance on the board, there is a temporary charge at the port after the level is switched to open circuit, and the temporary charge causes a large delay between the control signal and the processed TTL signal

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