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Layout generation method of read-only memory

A read-only memory and layout technology, which is applied in the direction of instruments, special data processing applications, electrical digital data processing, etc., can solve the problems of low difficulty in storing information and poor security, and achieve the effect of improving security and increasing difficulty

Active Publication Date: 2016-11-02
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In the existing ROM layout generation method, the through-hole programming ROM only arranges the through holes inside the memory cell array, and the storage order of different code points of different customers in the same ROM is the same. For the generated read-only memory layout, it is less difficult for a third party to perform reverse physical cracking to obtain the stored information, and the security is poor

Method used

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  • Layout generation method of read-only memory
  • Layout generation method of read-only memory
  • Layout generation method of read-only memory

Examples

Experimental program
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Effect test

Embodiment 1

[0033] ROM layout generation methods such as Figure 4 shown, including the following steps:

[0034] 1. In the column address decoding layout, set the column decoding metal line 501, the bit line selection tube control signal metal line 505, and obtain the column address decoding layout after the decoding wiring, as shown in FIG. Figure 5 , Figure 6 shown

[0035] The column decoding metal line 501 crosses the bit line selection transistor control signal metal line 505;

[0036] 2. In the decoding layout of the column address after the decoding wiring, one of the multiple intersections of each column decoding metal line 501 and a plurality of bit line selection transistor control signal metal lines 505 is randomly selected to place the column decoding pass The hole 502 is used to obtain the decoding layout of the column address after the through hole;

[0037] A column decoding through hole 502 is placed at the intersection of the column decoding metal line 501 and the ...

Embodiment 2

[0044] Based on Embodiment 1, in step 1, in the column address decoding layout, a column decoding metal line 501, a redundant column decoding metal line 503, and a bit line selection transistor control signal metal line 505 are arranged to obtain a column after decoding and wiring. Address decoding layout;

[0045] The column decoding metal line 501, the redundant column decoding metal line 503 and the bit line selection transistor control signal metal line 505 intersect;

[0046] The column decoding metal line 501 is parallel to the redundant column decoding metal line 503 and has the same specifications;

[0047] In step 2, in the decoding layout of the column address after the decoding wiring, one of the multiple intersections of each column decoding metal line 501 and a plurality of bit line selection transistor control signal metal lines 505 is randomly selected to place the column address Code through hole 502, each redundant column decoding metal line 503 and a plurali...

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Abstract

The invention discloses a read-only memory layout generation method including steps of reserving a column decoding metal wire programmable via layout on a read-only memory layout, adding redundant column metal wires, arranging column addresses randomly according to the position-programmable via layout, and changing physical position of layout of codes in the read-only memory correspondingly. Therefore, the law of physical sequence of the vias of a memory unit array of each via mask read-only memory is broken through, the difficulty in cracking memory content reversely through the read-only memory layout is increased, and security of the read-only memory is improved.

Description

technical field [0001] The invention relates to semiconductor integrated circuit circuit design technology, in particular to a read-only memory layout generation method. Background technique [0002] Through-hole mask ROM cells such as figure 1 As shown, the through-hole mask read-only memory unit 101 is an NMOS, wherein the gate of the NMOS is connected to the WL (word line) signal to control the opening and closing of the NMOS; the source and the substrate of the NMOS are grounded, and the drain passes through the through hole The switch 100 is connected to the BL (bit line) signal. If the through hole of the read-only memory unit exists, the code is "0"; if the read-only memory unit does not have a through hole, the code is "1"; vice versa. [0003] The common layout structure of read-only memory single-bit output circuit is as follows: figure 2 As shown, the column address decoding circuit and the row address decoding circuit are jointly controlled to transmit the el...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 杨光华
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP