Method for implementing quick locating and wiring of field programmable gate array (FPGA)

Abstract

The invention discloses a method for implementing quick locating and wiring of a field programmable gate array (FPGA). The method includes: applying annealing function to temperature updating of the FPGA; adopting repeated annealing processes to acquire current_best, the best solution which can be found out in each annealing process, and performing the next annealing process; adopting an initialized wiring method taking load balance into consideration, assuming P to be the number of processors, establishing P threads, dividing a chip into P areas, and dividing signals into task sets of the threads in areas; adopting multi-thread and executing wiring iteration, and the P threads concomitantly looking for most suitable paths currently for the signals in the task sets according to a parallelized A* addressing algorithm; adopting a heavy wiring crowded signal method to complete the one-time wiring iteration. By the method, the wiring process is quickened, and locating and wiring is obviously quickened under the condition that two important performance indexes of delay and thread length of a final circuit are basically remained unchanged.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a method for realizing fast layout and wiring of a field programmable gate array. Background technique [0002] In recent years, with the rapid development of integrated circuit technology, Field Programmable Gate Array (FPGA), because of its high integration, rich logic resources, flexible design and reconfigurability, is widely used in aerospace and national defense fields. Widely, my country needs to import a large number of Field Programmable Gate Array (FPGA) chips and supporting software from abroad every year, while the domestic Field Programmable Gate Array (FPGA) industry needs to be developed, which restricts the development of the domestic Field Programmable Gate Array (FPGA) industry. , mainly due to the lack of self-developed high-performance and high-quality Field Programmable Gate Array (FPGA) design software. [0003] The design process of Field Progr...

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Problems solved by technology

[0008] The purpose of the embodiment of the present invention is to provide a method for realizing fast layout and wiring of field programmable gate array, aiming at solving the problems of long CPU time consumption and low efficiency in the layout and wiring process of existing field programmable gate array

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