Embedded electromagnetic shielding package structure with high heat dissipation chip and manufacturing method thereof

Abstract

A high heat dissipation chip-embedded electromagnetic shielding packaging structure and a manufacturing method thereof, the packaging structure includes a metal carrier (1), a chip (2) is mounted on the surface of the metal carrier (1), and the chip (2 ) is provided with shielding copper pillars (8), the surface of the chip (2) is soldered with copper balls (3), the copper balls (3) are flush with the insulating material (4), and the copper balls (3) and The surface of the insulating material (4) is provided with a metal circuit layer (5), the outer periphery of the metal circuit layer (5) is encapsulated with a photosensitive material (7), and the surface of the metal circuit layer (5) is provided with metal balls (6). The beneficial effects of the present invention are: it mounts the chip on the surface of the carrier board, puts copper balls on the PAD by ball bonding or makes copper pillars on the chip PAD, and after molding and encapsulating, the copper balls or copper pillars are thinned and rewired. It is connected to the external pins, and the chip has a heat sink, which can provide efficient heat dissipation, so as to achieve high-performance electrical connection and good reliability guarantee.

Description

technical field [0001] The invention relates to a high heat dissipation chip embedded electromagnetic shielding packaging structure and a manufacturing method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] The current chip size packaging (CSP) process mainly includes: [0003] 1. The chip is first mounted on the lead frame or substrate and then bonded on the surface of the chip, or the surface of the chip is secondary wired to make bumps and then flipped on the lead frame or substrate before molding and encapsulation and subsequent processes; [0004] 2. After secondary wiring on the chip surface, make solder balls at the wiring layer Pad, and then perform molding encapsulation (or bare chip) and subsequent processes. [0005] The current chip size packaging (CSP) process has the following deficiencies and defects: [0006] 1. As the requirements for small, thin, and high-density products continue to increase, lead frame...

AI Technical Summary

Problems solved by technology

[0006] 1. As the requirements for small, thin, and high-density products continue to increase, lead frames or substrates are required to be small, thin, easy to deform, and difficult to manufacture;

[0007] 2. Products using wire bonding technology are limited by the arc height and arc length of the welding wire, so the thickness and size of the product cannot be made very small;

[0008] 3. For products using flip-chip technology or wafer-level packaging, the chip needs secondary wiring to make bumps, and the initial manufacturing cost is relatively high;

[0010] 5. Underfill is used in most flip-chip products, its function is to relieve the shear stress caused by the difference in coefficient of thermal expansion (CTE) between the chip and the substrate, but there are problems of insufficient filling and voids;

[0011] 6. The product is easily interfered by external electromagnetic signals during operation, and the electromagnetic waves generated by itself are easy to radiate other devices to cause adverse phenomena and poor stability

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