Multi-core processor soft error pressure test program generating system and method

A multi-core processor, stress testing technology, applied in the field of processors, which can solve problems such as architectural type restrictions, the use of a large number of different test programs, etc.

Inactive Publication Date: 2014-07-02
SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI
View PDF1 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The present invention provides a multi-core processor soft error stress test program generation system and method, aiming to solve the existing soft error detection and recovery methods to detect the range value of the soft error occurrence rate of a certain architecture type processor , a technical problem requiring the use of a large number of different test programs and limited by the type of architecture

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-core processor soft error pressure test program generating system and method
  • Multi-core processor soft error pressure test program generating system and method
  • Multi-core processor soft error pressure test program generating system and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0036] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0037] see figure 1 , is a schematic structural diagram of a system for generating a multi-core processor soft error stress test program according to an embodiment of the present invention. The multi-core processor soft error stress test program generating system according to the embodiment of the present invention includes a code generator, a multi-core processor simulator, an arbitration module and a machine learning module connected in sequence. Wherein, the connection includes a physical connection, an electrical connection, or a signal connection.

[0038] The code generator generates the AV...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention belongs to the technical field of processors and particularly relates to a multi-core processor soft error pressure test program generating system and method. The system comprises a code generator, a multi-core processor simulator, an arbitrating module and a machine learning module. The code generator generates a multi-core processor system structure weakness factor limit test program according to control parameters. The multi-core processor simulator operates the limit test program to generate system structure weakness factor values. The arbitrating module judges whether the multi-core processor system structure weakness factor limit test program generated by the code generator accords to requirements or not. The machine learning module is used for operating a genetic algorithm tool to optimize the control parameters of the code generator. The system has the advantages that the generated AVF limit test program can detect the maximum value of soft error occurrence rate in one system structure to the maximum extent, and searching and modifying a benchmark test program are omitted.

Description

technical field [0001] The invention belongs to the technical field of processors, and in particular relates to a system and method for generating a multi-core processor soft error stress test program. Background technique [0002] Moore's Law states that when the price remains constant, the number of transistors that can be accommodated on an integrated circuit will double approximately every 18 months, and the performance will also double. However, the emergence of each new technology will bring new technical problems and hinder the promotion and application of emerging technologies. "Soft error" is a kind of "transient error" that occurs in the case of shrinking manufacturing process dimensions. This kind of error makes the development of the processor face serious challenges, making the processor fragile and more susceptible to environmental influences. [0003] This "momentary error" is caused by the flipping of a bit in a digital circuit, which is attributed to tiny ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
Inventor 喻之斌须成忠卓文伟
Owner SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap