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Manufacturing method of electronic component packaging

An electronic component and manufacturing method technology, which is applied in the field of electronic component packaging manufacturing method, can solve problems such as the thickness of the overall structure, and achieve the effect of thinning the thickness and reducing the production cost.

Active Publication Date: 2016-12-28
UNIMICRON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, the above-mentioned existing manufacturing methods can only form electronic component packages with symmetry and a build-up structure of 4 circuit layers, so the overall structure is relatively thick

Method used

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  • Manufacturing method of electronic component packaging
  • Manufacturing method of electronic component packaging
  • Manufacturing method of electronic component packaging

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0071] like Figure 2A to Figure 2M What is shown is a schematic cross-sectional view of the first embodiment of the manufacturing method of the electronic component packaging of the present invention.

[0072] like Figure 2A As shown, a carrier board 20 is provided, which includes a stacked substrate 201 and a substrate dielectric layer 202 , and the opposite surfaces of the substrate 201 may have metal layers (not shown).

[0073] like Figure 2B As shown, a first metal layer 20 a is formed on the base dielectric layer 202 .

[0074] like Figure 2C As shown, a first dielectric layer 21 is formed on the first metal layer 20a, and a second metal layer 21a is also formed on the first dielectric layer 21.

[0075] like Figure 2D As shown, at least one opening 211 is formed in the first dielectric layer 21 through the first dielectric layer 21 and the second metal layer 21a to expose part of the first metal layer 20a, and the opening 211 is formed. For laser ablation.

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no. 2 example

[0086] like Figure 3A to Figure 3O The one shown is a schematic cross-sectional view of the second embodiment of the manufacturing method of the electronic component packaging of the present invention.

[0087] like Figure 3A As shown, a carrier board 30 is provided, which includes a laminated substrate 301 and a substrate dielectric layer 302 , and the opposite surfaces of the substrate 301 may have metal layers (not shown).

[0088] like Figure 3B As shown, a first metal layer 30 a is formed on the substrate dielectric layer 302 .

[0089] like Figure 3C As shown, a plurality of electrical connection pads 30b are formed on the first metal layer 30a.

[0090] like Figure 3D As shown, a first dielectric layer 31 is formed on the first metal layer 30 a and the electrical connection pad 30 b, and a second metal layer 31 a is formed on the first dielectric layer 31 .

[0091] like Figure 3E As shown, at least one opening 311 is formed through the first dielectric lay...

no. 3 example

[0103] like Figure 4A to Figure 4M The one shown is a schematic cross-sectional view of the third embodiment of the manufacturing method of the electronic component packaging of the present invention.

[0104] like Figure 4A As shown, a carrier board 40 is provided, which includes a laminated substrate 401 and a substrate dielectric layer 402 , and the opposite surfaces of the substrate 401 may have metal layers (not shown).

[0105] like Figure 4B As shown, a first metal layer 40 a is formed on the substrate dielectric layer 402 .

[0106] like Figure 4C As shown, a first dielectric layer 41 is formed on the first metal layer 40 a, and a second metal layer 41 a is formed on the first dielectric layer 41 .

[0107] like Figure 4D As shown, the second metal layer 41a is patterned to expose the first dielectric layer 41, and the patterned second metal layer 41a forms the third wiring layer 41b.

[0108] like Figure 4E As shown, at least one opening 411 is formed thr...

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Abstract

A preparation method for an electronic component package comprises the following steps: providing a bearing plate, wherein a first metal layer is formed on one surface of the bearing plate; forming a first dielectric layer on the first metal layer; forming a second metal layer on the first dielectric layer and patterning the second metal layer to expose the first dielectric layer; forming at least one opening penetrating through the first dielectric layer in the first dielectric layer to expose part of the first metal layer; arranging at least one electronic component in the opening; forming a second dielectric layer on the first dielectric layer and the electronic component; forming a plurality of blind holes penetrating through the second dielectric layer and exposing the electronic component in the second dielectric layer; forming a circuit layer electrically connected with the electrical component on the second dielectric layer and in the blind holes; and removing the bearing plate. By adopting the method of the invention, the overall thickness of the electronic component package can be reduced, and the cost of the preparation process can be lowered.

Description

technical field [0001] The invention relates to a method for manufacturing electronic component packaging, in particular to a method for manufacturing electronic component packaging that can reduce the thickness of the electronic component package. Background technique [0002] Technology is rapidly developing, and the development trend of electronic products is to make products thinner and smaller. Therefore, we continue to develop electronic component packaging manufacturing technologies that can keep up with the current technological trends, and in order to make electronic component packaging more effective. Application, still continuously improving the process technology of electronic component packaging. [0003] see Figure 1A to Figure 1H , which is a schematic cross-sectional view of a conventional electronic component packaging method. [0004] like Figure 1A As shown, a core board 10 is provided, and a conductive metal layer 10a is formed on the core board 10, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L21/60
CPCH01L24/19H01L21/568H01L2224/04105H01L2224/19H01L2224/73267H01L2224/92244H01L2924/00012
Inventor 陈昌甫赖文隆陈君豪
Owner UNIMICRON TECH CORP