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Array substrate, manufacturing method thereof and display device

A technology of an array substrate and a manufacturing method, applied in the display field, can solve problems such as poor fog, affecting product quality, Ioff, etc., and achieve the effects of avoiding pollution, avoiding deterioration of TFT characteristics, and improving product quality

Inactive Publication Date: 2014-07-16
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But H 2 Plasma will cause the ITO of the first transparent electrode to be reduced, resulting in foggy defects
Therefore, in the existing H-ADS display mode TFT array substrate preparation process, H cannot be used before the passivation layer 180 is deposited (PVX Dep). 2 Plasma processing, resulting in TFT I off Higher, affecting product quality

Method used

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  • Array substrate, manufacturing method thereof and display device
  • Array substrate, manufacturing method thereof and display device
  • Array substrate, manufacturing method thereof and display device

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Embodiment Construction

[0051] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0052] Such as Figure 2a ~ 2g As shown, the method for fabricating an array substrate in this embodiment includes the following steps:

[0053] Step one, such as Figure 2aAs shown, a pattern including a gate line (not shown in the figure), a gate 220, a common electrode line 230 and a gate insulating layer 240 is formed on the base substrate 210 (the gate 220, the gate line and the common electrode line 230 are formed at the same time Formed in the patterning process, only one mask is needed). The gate insulating layer 240 is formed on the gate line, the gate electrode 220 and the common electrode 230 . The specific process flow and the formed graphic structure of th...

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Abstract

The invention relates to the technical field of displaying, and discloses a manufacturing method of an array substrate. The manufacturing method comprises the steps that a pattern comprising a grid electrode, a grid line, a common electrode line and a grid insulating layer is formed on a substrate body; a pattern comprising a data line, a source electrode, a drain electrode and an active layer is formed; a pattern comprising an insulating spacer layer is formed on the pattern comprising the source electrode, the drain electrode and the active layer; a pattern comprising a first transparent electrode is formed on the insulating spacer layer; a pattern comprising a passivation layer is formed on the first transparent electrode; a pattern comprising a second transparent electrode is formed on the passivation layer. The invention further discloses the array substrate and a display device. The pollution to a TFT channel due to the ITO technology can be effectively avoided.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] Currently, the Advanced Super Dimension Switch (ADS) display mode has been widely developed due to its superior display quality, and has become an important technical standard in the global industry. Among them, the H-ADS (High Aperture Ratio ADS) mode is one of the most advanced processes. [0003] The existing H-ADS display mode thin film transistor (TFT) array substrate preparation process flow is as follows: Figure 1a and 1b As shown: forming a gate 120, a gate line (not shown in the figure) and a common electrode line 130 (1 mask) on a base substrate 110; forming a gate insulating layer 140; forming an active layer 150; forming a data line ( not shown in the figure), source 161 and drain 162 (1 mask); form first transparent electrode 170 (1 mask); form passivat...

Claims

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Application Information

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IPC IPC(8): H01L21/77H01L27/12
CPCH01L27/124H01L27/1259H01L27/1288H01L27/1248H01L27/127
Inventor 白金超丁向前刘耀李梁梁郭总杰
Owner BOE TECH GRP CO LTD
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