Communication method and system between FPGA and general processor

Abstract

The invention discloses a communication method and system between an FPGA and a universal processor. By means of the method, the FPGA is simulated to be an external SDRAM storage of the universal processor provided with an SDRAM controller, and accordingly synchronous data transmission between the FPGA and the universal processor is achieved. The method specifically includes the steps that the universal processor configures a mode register of an STI in the FPGA and sets a burst transmission length and a delay read cycle of the SDRAM controller; one end of the STI is connected with a storage module or a data processing unit in the FPGA, and the other end of the STI is connected with the SDRAM controller of the universal processor; the STI receives a synchronous signal sent by the SDRAM controller, then carries out logic decoding and conversion on the received synchronous signal and translates the synchronous signal into a signal mode capable of being used by a data storage or processing unit in the FPGA, and accordingly the universal processor can carry out write-in and read operation on the data of the data storage or processing unit in the FPGA through the SDRAM controller.

Description

Technical field [0001] The invention belongs to the field of circuit and signal system data transmission, and specifically relates to a communication method and system between an FPGA and a general-purpose processor. Background technique [0002] In the field of circuit and signal system data transmission, FPGAs and general-purpose processors generally use the external asynchronous bus interface of general-purpose processors for data communication. The advantage of using this interface method is that the interface is simple to implement and easy to operate, but the disadvantage is that the data transmission rate is low. Therefore, when the data transmission rate is high, this traditional asynchronous data transmission method between FPGA and general-purpose processor cannot meet the basic requirements of the application. Summary of the invention [0003] The purpose of the present invention is to overcome the above technical problems, the present invention provides a communicatio...

AI Technical Summary

Problems solved by technology

The advantage of using this interface method is that the interface is simple to implement and easy to operate, and the disadvantage is that the data transmission rate is low

Therefore, when the data transmission rate is required to be high, this traditional asynchronous data transmission method between the FPGA and the general-purpose processor cannot meet the basic needs of the application.

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