Embedded reconfigurable system based on large-scale coarse granularity and processing method of system

Abstract

The invention discloses an embedded reconfigurable system based on the large-scale coarse granularity and a processing method of the system. The system comprises a system bus, a configuration bus, an embedded microprocessor, a data memory, a reconfigurable processor, a reconfiguration controller, an interrupt controller and a direct memory access controller. According to the method, for a common matrix inversion algorithm, 4 special reconfigurable arrays and an on-chip data transmission unit are arranged in the reconfigurable processor; by mapping the matrix inversion algorithm on the reconfigurable arrays containing a plurality of basic operations, the operation parallelism degree is improved, so that the operation efficiency is improved. Meanwhile, the data exchange among the arrays is optimized through an on-chip data transmission network.

Description

technical field [0001] The invention relates to the field of embedded reconfigurable systems, in particular to a large-scale coarse-grained embedded reconfigurable system and a processing method thereof applied in the fields of radar and communication. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) have historically been the two dominant computing paradigms. With the continuous improvement of computing efficiency requirements, a reconfigurable computing technology that takes into account the flexibility of general-purpose processors and the high-efficiency of application-specific integrated circuits has begun to come into people's eyes. Reconfigurable computing technology can convert an algorithm into a data flow form through the configuration of the computing unit, improving computing efficiency. The large-scale coarse-grained dynamic reconfigurable processor mentioned here is a system-on-chip based on reconfig...

AI Technical Summary

Problems solved by technology

Compared with reconfigurable processors, such a process not only increases the time to read instructions, but also cannot perform parallel computing, resulting in low performance

Although the field programmable gate array also has high-efficiency computing speed, it lacks flexibility and cannot continue to complete the calculation of other algorithms after the design is completed.

At present, a variety of reconfigurable systems have been designed for matrix operations at home and abroad, which can effectively complete operations such as matrix addition and subtraction, matrix multiplication, and triangular matrix inversion, but have not been optimized for matrix inversion operations. There will be many flowing water bubbles, which will affect the computing efficiency

At the same time, most of the existing reconfigurable systems can only complete matrix operations below the 4th order. For large-scale matrices, matrix inversion operations can only be completed through matrix decomposition, which will greatly reduce operational efficiency.

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