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A protection method and system for multi-chip interconnection and interlocking

A protection system, multi-chip technology, applied in the protection method and system field of multi-chip interconnection and interlock, can solve problems such as system failure, and achieve the effect of solving system failure

Active Publication Date: 2017-03-15
SHENZHEN KSTAR SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention provides a protection method for multi-chip interconnection and interlocking, aiming to solve the problem of system failure caused by software matching

Method used

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  • A protection method and system for multi-chip interconnection and interlocking
  • A protection method and system for multi-chip interconnection and interlocking
  • A protection method and system for multi-chip interconnection and interlocking

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Embodiment Construction

[0045] figure 1 , 2 It shows the soft and hard control node detection flow chart in the multi-chip interconnection and interlock protection method provided by the present invention, which is described in detail as follows:

[0046] The protection and self-inspection process of the soft control node is as follows:

[0047] In step S1, after the device is powered on, the soft control node prepares to perform an automatic inspection on itself.

[0048] In step S2, before the soft-control node starts to automatically check itself, the soft-control node prohibits the power semiconductor drive and clears all interactive data with the external control node; in order for the soft-control node to perform better self-check, The soft control node forbids all semiconductor drivers and channels for exchanging data with the outside world, so that it can complete automatic detection without being affected by external data.

[0049] In step S3, the soft control node of the device automatic...

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Abstract

The invention relates to a method for protection of multi-chip interconnection and interlocking. The method is characterized by comprising the following steps that A, all functions of a software control node and a hardware control node are automatically detected; B, whether the function states of the software control node and the hardware control node are normal or not is judged; C, a firmware version feature code of the hardware control node is extracted and sent to the software control node, high resistance bus parallel operation is conducted, and driving of a power semiconductor is forbidden; D, whether a received firmware version is compatible with the hardware control node or not is judged; E, whether the hardware control node is compatible with all received node versions and the version of the hardware control node or not is judged, power is supplied, the system state is detected, and a system is protected in the failure state when a CPLD / FPGA is powered on or the version is not matched; after software of the CPLD / FPGA or an MCU / DSP is updated, a compatibility detection strategy is provided, and system failure caused by unmatched software is avoided.

Description

technical field [0001] The invention belongs to the field of chip protection, and in particular relates to a multi-chip interconnection and interlocking protection method and system. Background technique [0002] In the multi-chip solution, MCU / DSP and other microprocessors may run away due to the abnormality of software execution, which may cause the drive of the power semiconductor by mistake or cause its drive to be abnormal, resulting in damage to the power semiconductor. What's more serious is that in the parallel system, if the unit where the abnormal MCU / DSP is located is not separated from the parallel system, it may even cause the parallel system to collapse. [0003] The basic unit of the CPLD / FPGA actuator is a combination of flip-flops and logic gates. Basically, there will be no abnormal running of the programs of microprocessors such as MCU / DSP. Therefore, a common solution is to use CPLD / FPGA to perform MCU / DSP The supervisor, when its exception is raised, bl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F21/57
CPCG06F21/572
Inventor 刘程宇万学维
Owner SHENZHEN KSTAR SCI & TECH