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Obstacle bypassing wiring method based on optimization of shortest wire length in large-sized integrated circuit design

A large-scale integrated circuit and wiring method technology, which is applied in computing, electrical digital data processing, special data processing applications, etc., can solve the problems of increasing the number of pins and increasing the difficulty of wiring, and achieves effective wiring methods with short wire lengths. , the best effect

Inactive Publication Date: 2014-08-13
FUZHOU UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, the number of pins that need to be interconnected is also increasing, making wiring more difficult.

Method used

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  • Obstacle bypassing wiring method based on optimization of shortest wire length in large-sized integrated circuit design
  • Obstacle bypassing wiring method based on optimization of shortest wire length in large-sized integrated circuit design
  • Obstacle bypassing wiring method based on optimization of shortest wire length in large-sized integrated circuit design

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Embodiment Construction

[0032] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0033] The specific description of the wiring problem in the embodiment of the present invention is as follows:

[0034]Given the wire mesh information and obstacle information, the given wire mesh information includes the two-dimensional coordinate information of each wire mesh pin on the plane, and the given obstacle information includes the four corners of each rectangular obstacle (4 vertex) on the two-dimensional coordinate information on the plane; the pin is required not to fall inside the obstacle, but can be on the boundary of the obstacle; it is required that two obstacles will not overlap each other, but can be adjacent on the boundary; the problem goal is , construct a Steiner tree composed of only horizontal and vertical lines without passing through any obstacles, and connect all the net pins to minimize the bus length.

[0035] ...

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Abstract

The invention relates to the technical field of the physical design of a large-sized integrated circuit, in particular to an obstacle bypassing wiring method based on the optimization of shortest wire length in the large-sized integrated circuit design. The method comprises the steps: establishing a wiring question map according to an escape map theory, marking top points, i.e., necessary points by adopting a multi-source parallel search method, establishing a feasible solution steiner tree on the basis of a necessary point set, and finally optimizing the feasible solution. The method is reasonable in wiring layout, the obtained wire length is short, and the wiring effect is good.

Description

technical field [0001] The invention relates to the technical field of physical design of large-scale integrated circuits, in particular to a method for circumventing obstacles based on the shortest optimization of line length in large-scale integrated circuit design. Background technique [0002] In the physical design of large-scale integrated circuits, under the Manhattan model, the routing method based on the shortest line length optimization is the most important basic work of overall routing and detailed routing in physical design. With the rapid development of integrated circuit technology, a large number of macro cells, IP modules, and pre-wiring nets have been introduced into modern integrated circuit design, resulting in a large number of rectangular obstacles on the wiring chip and the number is still increasing. At the same time, the number of pins that need to be interconnected is also increasing, making wiring more difficult. During the routing process, it is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 张浩叶东毅陈羽中余春艳张栋杨晶菁
Owner FUZHOU UNIV
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