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A kind of semiconductor device and its manufacturing method

A semiconductor and conductor layer technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as damage and affecting device yield

Active Publication Date: 2018-03-30
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Exceeding the thermal budget of the formed part on the device can cause damage and impact device yield

Method used

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  • A kind of semiconductor device and its manufacturing method
  • A kind of semiconductor device and its manufacturing method
  • A kind of semiconductor device and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] figure 1 A semiconductor device 10 is shown to include a substrate 12; the semiconductor device may include an array region 14 and an edge region 16; a well region 18 is formed in the substrate 12; the well region 18 of the embodiment includes an N-type deep well region (Deep N Well, DNW), for example, has a high implantation energy and a high voltage (high voltage, HV) well region.

[0046] figure 2 After forming oxide layer 20, nitride layer 22 and photoresist layer 24, the figure 1 The semiconductor device 10 in. The oxide layer 20 may be a pad oxide layer. The nitride layer 22 may be a silicon nitride layer and is provided over the oxide layer. Photoresist layer 24 may be any suitable photoresist. In the illustrated embodiment, the mask is of the "dark" type, wherein when the mask is present, the underlying structures are protected and not etched. Other types of masks, such as a reversed diffusion mask (RDF) can also be used. The use of a selective RDF mask ...

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PUM

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a stacked structure and a transistor; the substrate includes a first part and a second part; the stacked structure is formed on the substrate above the first region; a transistor structure having a gate is formed in the second region; a bottom of the gate structure is disposed at a height from the substrate which is smaller than the distance between the substrate and a bottom of the stacked structure a height between.

Description

technical field [0001] The present invention relates to a semiconductor device, including methods and structures for improving the manufacturing of semiconductor devices such as 3D memory devices. Background technique [0002] In the manufacture of semiconductor devices, different structures are arranged adjacent to each other during the formation of a complete device. For example, a 3D memory structure may include peripheral circuits and array circuits. Different conditions required for the formation of different structures may result in adverse effects on other structures. [0003] For example, the array region may be located in a channel provided in the substrate. Formation of such trenches, for example by reactive ion etching, may result in loading effects that increase process variation and affect device yield. [0004] As another example, array regions and edge regions (or different orientations thereof) may need to be exposed to effective temperatures for a non-neg...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L25/16
CPCH10B99/00H10B41/42H10B41/50H10B41/27H10B43/40H10B43/50H10B43/27
Inventor 赖二琨邱家荣罗杰
Owner MACRONIX INT CO LTD