Apparatus and methods for invertible sine-shaping for phase interpolation

Abstract

Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

Description

technical field [0001] Embodiments of the present invention relate to electronic devices, and more particularly to sinusoidal shaping filters and phase interpolators. Background technique [0002] Clock and data recovery (CDR) systems can be used in a variety of applications to recover data from high-speed serial data streams. For example, the CDR system can be used in communication systems, optical networks, and inter-chip communication. [0003] A CDR system can use a sampling clock signal to capture samples from a serial data stream. The sampling clock signal can be generated in a number of ways. For example, a CDR system may include a frequency synthesizer to generate a high-speed clock signal having a frequency several times that of a reference clock signal, and a CDR system may generate a quadrature square-wave clock signal from the high-speed clock signal by employing a quadrature frequency divider. A quadrature square wave clock signal can be filtered to generate ...

AI Technical Summary

Problems solved by technology

As the number of weights increases, the phase interpolator can become more difficult to design, consume a relatively larger amount of power, present a relatively larger load on the input driver, and / or occupy a larger die area

For example, interpolation buffers consume a lot of leakage energy, even when not active

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