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System and method for improving speed and power in a switched-capacitor amplifier

A technology of amplifiers and capacitors used in the field of digital-to-analog converters

Active Publication Date: 2014-09-17
ANALOG DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Traditional techniques have limitations in stable response due to non-dominant poles

Method used

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  • System and method for improving speed and power in a switched-capacitor amplifier
  • System and method for improving speed and power in a switched-capacitor amplifier
  • System and method for improving speed and power in a switched-capacitor amplifier

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Embodiment Construction

[0020] Figure 1A A conventional pipeline ADC is shown. Several low-resolution stages (stages 1, 2, ..., N) are cascaded to obtain a high overall resolution. Each stage runs in parallel and performs a rough analog-to-digital conversion, and computes its quantization error (as called "residue"). The quantization error is decomposed into a data aligner and combiner 102, which outputs a digital signal D OUT . The downside is that throughput is limited by the speed of a single stage. However, analog circuit non-idealities can be corrected by digital correction.

[0021] Figure 1B is available for Figure 1A Block diagram of a pipelined ADC for a conventional MDAC. This stage includes the MDAC shown within the dashed line. This MDAC has gain blocks GM (also known as "span-stage gain elements") for improving noise, subsequent matching and power dissipation in pipelined ADCs. However, as discussed above, G (the active gain block) is the main contributor to power consumption a...

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Abstract

A multiplying digital-to-analog converter ("MDAC") that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as "sampling capacitor") is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. The amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.

Description

technical field [0001] This invention relates to amplifiers and, more particularly, to improving speed and power in switched capacitor amplifiers, such as multiplying digital-to-analog converters (MDACs). Background technique [0002] Analog-to-digital converters (ADCs) are used in electronic equipment to convert analog signals to digital signals. ADCs can be designed in many different architectures. One sticky ADC architecture is the pipelined ADC. Such as Figure 1A As shown, a pipelined ADC operates on discrete-time signals, so the math, sample-and-hold, DAC, and gain can be performed in a single switched-capacitor circuit (such as an MDAC). MDAC is a high-gain and high-bandwidth amplifier using capacitive feedback. [0003] In analog design, the ideal is to reduce power consumption and maximize speed. However, in modern high-speed switched-capacitor CMOS pipeline ADCs, the MDAC is a major contributor to power consumption and clock-rate limitations. Whether single-st...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/06
CPCH03F3/005H03M1/164H03F3/45475H03F2203/45514
Inventor W·T·博莱斯M·R·埃里奥特
Owner ANALOG DEVICES INC