An improved fan-out wafer-level three-dimensional semiconductor chip packaging process

Abstract

The present invention provides an improved fan-out square chip-level three-dimensional semiconductor chip packaging process, which ensures the maximum processing size, improves production capacity, reduces production costs, and solves the effects of factors such as warpage in the manufacturing process, including The following steps: making an alignment mark on the carrier sheet; covering the carrier sheet with a temporary bonding material, attaching a thermally conductive material to the temporary bonding material; mounting a chip on the thermally conductive material, and coating the back of the chip or the thermally conductive material with adhesive; Coating the first type of insulating resin on the carrier sheet; opening a window on the first type of insulating resin to form a via hole; forming an electroplating circuit in the pattern area exposed by the photoresist; removing the seed layer electroplating circuit and the bottom of the electroplating circuit Seed layer; coating the first type of insulating resin, mounting the chip on the first type of insulating resin; forming a multi-layer chip stacking structure; coating the second type of insulating resin, opening a window corresponding to the chip on the second type of insulating resin; forming Solder balls; separate chips.

Description

technical field [0001] The invention relates to the technical field of microelectronic packaging technology, in particular to an improved fan-out square chip-level three-dimensional semiconductor chip packaging technology. Background technique [0002] With the trend of multi-function and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to cope with the development of a new generation of electronic products, especially the development of smart phones, PDAs, ultrabooks and other products, the size of chips is developing in the direction of higher density, faster speed, smaller size, and lower cost. The emergence of Fanout Panel Level Package (FOPLP), as an upgraded technology of Fanout Wafer Level Package (FOWLP), has a broader development prospect. [0003] See figure 1 , Japanese J-Devices company in CN 103247599A patent, has given a kind of m...

AI Technical Summary

Problems solved by technology

[0011] In view of the above problems, the present invention provides an improved fan-out square wafer-level three-dimensional semiconductor chip packaging process, which effectively ensures the maximum processing size, improves production capacity, and reduces production costs. A double-sided symmetrical structure is used in the production process , which offsets the problems of warpage, expansion and contraction caused by the performance difference between materials, and reduces the difficulty of process manufacturing

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