General permutation circuit structure with simple configuration of permutation rules
A circuit structure and rule technology, which is applied in the field of general replacement circuit structure, can solve the problem that the relationship between replacement rules and configuration information is not intuitive and clear, and achieve the effect of simple and clear relationship, reduced difficulty of use, and low cost
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Embodiment 1
[0052] A kind of position replacement circuit supporting 128-bit arbitrary replacement rules is realized by utilizing the general replacement circuit structure provided by the present invention with simple configuration of replacement rules, and its circuit structure diagram is as follows image 3 shown.
[0053] The replacement circuit includes five parts, which are source register module, 128-to-1 multiplexer, result register module, replacement rule register module and control module. In this example the value of n is 128, the value of m is 1, and the value of k is 7. Wherein, the source register module includes 128 source registers with a data bit width of 1 bit and a clock gate unit, the input of the clock gate unit is a clock signal (clk) and the first write enable control signal ( en1), the gated clock unit outputs a gated clock signal, and uses the gated clock signal as the clock signal of all source data registers in the source register module; each input channel por...
Embodiment 2
[0064] Utilize the simple general permutation circuit structure provided by the present invention to realize a sub-block permutation circuit supporting arbitrary permutation rules of 16 sub-blocks (block size is 4 bits), and its circuit structure is as follows Figure 4 shown.
[0065] The sub-block replacement circuit mainly includes five parts, namely, a source register module, a 16-to-1 multiplexer, a result register module, a replacement rule register module and a control module. The value of n is 16, the value of m is 4, and the value of k is 4 in this example. The source register module includes 16 source registers with a data bit width of 4 bits and a gated clock unit, the input of which is a clock signal (clk) and the first write enable control signal (en1) , the gated clock unit outputs a gated clock signal, and uses the gated clock signal as the clock signal of all source registers in the source register module, the data bit width of the data input port of the sourc...
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