EEPROM memory array and EEPROM

Abstract

An EEPROM memory array and an EEPROM. The EEPROM includes: a memory array; a row decoding circuit suitable for providing a voltage ranging from 6V to 8V to word lines which are connected to a to-be-erased memory unit, providing a voltage ranging from -6V to -8V to first controlling grid lines and second controlling grid lines which are connected to the to-be-erased memory unit and providing a 0V voltage to the word lines, the first controlling grid liness and the second controlling grid lines which are not connected to the to-be-erased memory unit; a column decoding circuit suitable for providing a bias voltage to bit lines, source lines which are connected to the to-be-erased memory unit and to a P-type well region in a sub memory array in which the to-be-erased memory unit is arranged and providing a 0V voltage to the bit lines and the source lines which are not connected to the to-be-erased memory unit and to the P-type well region in a sub memory array in which the to-be-erased memory unit is arranged, wherein the bias voltage is negative in value. By means of the EEPROM memory array and the EEPROM, a memory is improved in durability.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to an EEPROM storage array and the EEPROM. Background technique [0002] Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only Memory) is a semiconductor storage device with a byte as the minimum unit of modification, which can be electronically rewritten multiple times. figure 1 It is a schematic cross-sectional structure diagram of an existing EEPROM storage unit. The EEPROM storage unit includes: a P-type well region 100, the P-type well region 100 is located in a semiconductor substrate; an intermediate electrode 140 located above the P-type well region 100; symmetrically distributed on both sides of the intermediate electrode 140 The first storage bit and the second storage bit. Wherein, the first storage bit includes a drain 111 , a first floating gate 121 and a first control gate 131 ; the second storage bit includes a sour...

AI Technical Summary

Problems solved by technology

[0011] What the present invention solves is the problem of low durability of EEPROM

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