Electron beam defect scanning device and method

Abstract

The invention discloses an electron beam defect scanning apparatus, for carrying out electron beam defect scanning on a wafer before preparation of an antireflective layer. The apparatus comprises: an electron beam defect scanner bench; a conductive pedestal which is for bearing a wafer has electron beam defect scanning performed thereon and is grounded to eliminate negative charge residual on the wafer; a transmission mechanism which is used for transmitting the wafer to the electron beam defect scanner bench from a wafer transmission box, transmitting the wafer to the conductive pedestal after the electron beam defect scanning from the electron beam defect scanner bench and transmitting the wafer back to the wafer transmission box after the negative charge residual on the wafer is eliminated; and a control mechanism for controlling the motion of the transmission mechanism. According to the invention, damage caused by the negative charge residual on the surface of the wafer to the antireflective layer due to the electron beam defect scanning can be eliminated.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an electron beam defect scanning device and an electron beam defect scanning method. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the line width of product devices is constantly decreasing, and defects will cause greater damage to product yield. Therefore, improving the ability to capture chip defects has become an important means to improve semiconductor yield. [0003] Flash products have a storage area and a logic operation area. The storage area and the logic operation area generally use shallow trenches of different depths to isolate STI, and the formation of the STI trench is realized through two photolithographic etching processes. Specifically, the STI of the storage area is first formed by the first photolithography etching, and then the bottom anti-reflection layer BARC is formed, and the STI of ...

AI Technical Summary

Problems solved by technology

During the photolithography and etching process of the STI in the subsequent logic operation area, the damage causes pit defects at the bottom of the STI trench, and the pit defects will directly affect the formation of the STI structure, thereby affecting the normal operation of the MOS transistor

In the prior art, it is often used to avoid electron beam defect scanning before the formation of the BARC layer, so that the defect monitoring can be controlled at the subsequent site. Although this method can temporarily eliminate the damage to the BARC layer caused by the negative charge left by the electron beam defect scanning , but it is impossible to detect the abnormality of the STI trench photolithography in the storage area in time, and it cannot be remedied if there is a defect

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