Time domain reinforcement latch based on protection doors

Abstract

The invention relates to the radiation hardened integrated circuit design filed, and aims at providing a latch which is designed for reinforcement, can resist multiple inner node overturn, and can further resist transient pulses on an input port and a clock line. The technical scheme includes that the latch is a time domain reinforcement latch based on protection doors, the time domain reinforcement latch based on the protection doors is composed of six transmission gates from TG1 to TG6, three phase inverters from INV1 to INV3, three double input protection doors from DIG1 to DIG3, a three input protection door and a delay unit, wherein input ends D1, D2 and D3 feed signals to the corresponding double input protection doors DIG1, DIG2 and DIG3 after sequentially and correspondingly passing through the transmission gates TG1, TG2 and TG3, and the delay unit is arranged at an arbitrary position in an arbitrary output node A or B or C or in an arbitrary input end D1 or D2 or D3. The time domain reinforcement latch based on the protection doors is mainly used in radiation hardened integrated circuit design.

Description

technical field [0001] The invention relates to the field of anti-radiation integrated circuit design, in particular to a protection gate-based time domain hardened latch. Background technique [0002] For digital circuits used in space environments, especially sequential circuits, the occurrence of SEU will seriously affect the correctness of chip functions. Most of the existing hardening technologies are aimed at SEU. However, with the reduction of the size of integrated circuits and the reduction of chip power supply voltage, the amount of key charges that can be stored in the internal nodes of the circuit is greatly reduced, and the probability of MBU occurrence is gradually increasing. The occurrence of SET on the clock line and input port will also be transmitted to the circuit, affecting the performance of the circuit. The latch is the most commonly used storage unit in the circuit, and it is especially important for the reinforcement of the latch. Commonly used de...

AI Technical Summary

Problems solved by technology

However, with the reduction of integrated circuit size and the decrease of chip power supply voltage, the amount of key charges that can be stored in the internal nodes of the circuit is greatly reduced, and the probability of MBU occurrence is gradually increasing.

The occurrence of SET on the clock line and input port will also be transmitted to the circuit, affecting the performance of the circuit

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