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Radiation-resistant latch based on three-input protective gate

A protection gate, three-input technology, applied in the field of circuit design, anti-radiation integrated circuit design, can solve the problems of increasing circuit delay and power consumption, increasing circuit area, etc., to achieve the effect of reducing circuit area and power consumption

Inactive Publication Date: 2014-12-24
TIANJIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method will greatly increase the circuit area, which also increases the circuit delay and power consumption.

Method used

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  • Radiation-resistant latch based on three-input protective gate
  • Radiation-resistant latch based on three-input protective gate
  • Radiation-resistant latch based on three-input protective gate

Examples

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Embodiment Construction

[0014] use as figure 1 The circuit configuration shown. The latch structure includes 6 transmission gates TG1~6, 3 inverters INV1~3, 3 double input guard gates (Double Input Guardgate, DIG) DIG1~3 and a triple input guard gate (Trible Input Guardgate, TIG). It has three identical input signals D1, D2, and D3, which are sent to the latch through switches TG1, TG2, and TG3 respectively. D1 and D2 are used as the input of DIG1, ​​and the output A of DIG1 is connected to one of its input terminals D1 through an inverter INV1 and a switch TG4. Similarly, D2 and D3 are used as the input of DIG2, and the output B is connected to D2 through the inverter INV2 and TG5. D1 and D3 are used as the input of DIG3, and the output C is connected to D3 through the inverter INV3 and TG6. A, B, and C are used as input signals of TIG, and Q is output. where DIG (such as figure 2 (a) shows its transistor-level structure, (b) its logic symbol, (c) its timing diagram) using two PMOS and two NM...

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Abstract

The invention relates to the field of radiation-resistant integrated circuit design, provides a latch capable of resisting multi-node turnover and simple in structure, and discloses a radiation-resistant latch based on a three-input protective gate. According to the technical scheme, the radiation-resistant latch based on the three-input protective gate is composed of six transmission gates TG1-6, three phase inverters INV1-3, three two-input protective gates DIG1-3 and the three-input protective gate. Three same input signals are input to the input end D1, the input end D2 and the input end D3 correspondingly. The output B of the two-input protective gate DIG2 is connected to the input end D2 through the phase inverter INV2 and the transmission gate TG5. The input end D1 and the input end D3 serve as the input of the two-input protective gate DIG3. The output C of the two-input protective gate DIG3 is connected to the input end D3 through the phase inverter INV3 and the transmission gate TG6. The output A, the output B and the output C serve as input signals of the three-input protective gate TIG, and the output of the three-input protective gate TIG is Q. The radiation-resistant latch based on the three-input protective gate is mainly applied to the radiation-resistant integrated circuit design.

Description

technical field [0001] The invention relates to the field of anti-radiation integrated circuit design, in particular designed to use two-input protection gates and three-input protection gates to reinforce sequential circuits so that they can resist single event upset (Single event upset, SEU) and multiple-bit upset (Multiple-bit circuit design of the capability of upset, MBU). Specifically, it relates to a radiation-resistant latch based on a three-input protection gate. Background technique [0002] For digital circuits used in space environments, especially sequential circuits, the occurrence of single event upsets will seriously affect the correctness of chip functions. Most of the existing hardening technologies are aimed at SEU, but with the reduction of integrated circuit size and the decrease of chip power supply voltage, the amount of key charge that can be stored in the internal nodes of the circuit is greatly reduced, which gradually increases the probability of ...

Claims

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Application Information

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IPC IPC(8): H03K19/094
Inventor 徐江涛闫茜姚素英聂凯明史再峰高志远
Owner TIANJIN UNIV
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