High-speed ADC parallel-serial conversion circuit

A serial conversion and circuit technology, which is applied in the field of high-speed ADC parallel-serial conversion circuit, can solve the problems of high production cost and large occupied area, and achieve the effect of reducing circuit power consumption, circuit area and power consumption

Pending Publication Date: 2021-05-28
安徽芯纪元科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the implementation of the existing parallel-to-serial conversion circuit, when n channels of parallel data are input, n flip-flops and n switches need to be con

Method used

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  • High-speed ADC parallel-serial conversion circuit
  • High-speed ADC parallel-serial conversion circuit

Examples

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Example Embodiment

[0018]Example 1

[0019]A high speed ADC and string conversion circuit, including a clock reset management unit, n timing control unit, and data selection output unit, the present embodiment as N = 4 as an example, a specific structurefigure 1 .

[0020]The clock reset management unit CRMU provides clock signals and reset signals for each timing control unit, and the clock block diagram is likefigure 2 As shown, the main clock CLK produces a channel working clock CLK_DIG_MASTER_CH2, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3, CLK_DIG_MASTER_CH3. Four-channel operation clock generated by frequency division, respectively, after 2 clk_dig_sar_i_ch1, clk_dig_sar_i_ch2, ​​clk_dig_sar_i_ch3, clk_dig_sar_i_ch4; after 2 frequency and phase generating clk_dig_sar_q_ch1, clk_dig_sar_q_ch2, ​​clk_dig_sar_q_ch3, clk_dig_sar_q_ch4.

[0021]The channel working clock of each timing control un...

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Abstract

The invention provides a high-speed ADC parallel-serial conversion circuit, which comprises a clock reset management unit, n time sequence control units and a data selection output unit, and is characterized in that the clock reset management unit provides a clock signal and a reset signal for each time sequence control unit; each time sequence control unit is used for sampling, correcting and interleaving output of i-path data and q-path data in the respective channel, and the data selection output unit is used for interleaving and outputting the sampling data of each channel according to the output time sequence of the data of each channel. According to the parallel-serial conversion circuit, parallel-serial conversion from multi-path parallel m-bit data to single-path m-bit data can be achieved, conversion from a low sampling data rate to a high sampling data rate is completed, and compared with an implementation mode of an existing parallel-serial conversion circuit, the circuit area and power consumption are effectively reduced.

Description

technical field [0001] The invention relates to the technical field of parallel-serial conversion circuits, in particular to a high-speed ADC parallel-serial conversion circuit based on a synchronous sequential logic circuit. Background technique [0002] The rapid development of computer technology, communication technology and microelectronic technology has greatly promoted the development of ADC technology. As a key component of the interface between analog and data, ADC is widely used in various fields and plays an important role in information technology. ADC, like a computer, has experienced a development process from low speed to high speed. ADC low-speed (conversion time greater than 300us) structure has integral type, ramp type, tracking type; ADC medium-speed (conversion time is 1-300us) structure has successive approximation type; ADC high-speed (conversion time is less than 1us) structure has flicker type, partitioned, and high-resolution sigma-delta structures...

Claims

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Application Information

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IPC IPC(8): H03M9/00
CPCH03M9/00
Inventor 王媛李冬胡孔阳莫啸章钰刘先博
Owner 安徽芯纪元科技有限公司
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