Anti-radiation latch employing four-input guard gate

A protection gate, four-input technology, applied in electrical components, logic circuits, pulse technology, etc., can solve problems such as affecting circuit performance, and achieve the effect of reducing propagation delay and layout area.

Inactive Publication Date: 2014-12-17
TIANJIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Most of the existing reinforcement technologies are aimed at SEU, but with the reduction of integrated circuit size and the decrease of chip power supply voltage, the probability of MBU occurrence is gradually increasing, thus affecting the performance of the circuit

Method used

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  • Anti-radiation latch employing four-input guard gate
  • Anti-radiation latch employing four-input guard gate
  • Anti-radiation latch employing four-input guard gate

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Embodiment Construction

[0013] The structure of the latch of the present invention uses 7 transmission gates TG1-7, 3 inverters INV1-3, 3 two-input protection gates DIG1-3 and one FIG. It has four same input signals as D1, D2, D3, and D4, which are respectively sent to the latches through switches TG1, TG2, TG3, and TG4. D1 and D2 are used as the input of DIG1, ​​and the output A of DIG1 is fed back to one of its input terminals D1 through an inverter INV1 and a switch TG5. Similarly, D2 and D3 are used as the input of DIG2, and the output B is fed back to D2 via INV2 and TG6. D1 and D3 are used as the input of DIG3, and the output C is fed back to D3 through INV3 and TG7. A is connected to PM4 and NM4 of the FIG structure, B is connected to PM3 and NM3, C is connected to PM2 and NM2, PM1 is connected to the clock signal CK, and NM1 is connected to the inverse NCK of the clock signal. The output is Q. where DIG (such as figure 2 (a) shows its transistor-level structure, (b) its logic symbol, (c)...

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Abstract

The invention relates to the field of design of anti-radiation integrated circuits, and provided a latch capable of being applied to a radiation environment. The latch can resist SEU (Single Event Upset) and some MBU (Multiple Bit Upset). The latch is characterized in that when a storage node and an input signal of the latch are subjected to double bit upset due to particle bombardment, the charge deposited on a sensitive node can be released through the guard gate, thus the storage state of the latch can be maintained, and an accurate level signal can be transmitted into a post-stage circuit. According to the technical scheme, the anti-radiation latch employing the four-input guard gate comprises seven transmission gates TG1-6, three phase inverters INV1-3, three double input guard gates (DIG) 1-3, and a four-input guard gate. The anti-radiation latch employing the four-input guard gate is mainly applied to the design of the anti-radiation integrated circuit.

Description

technical field [0001] The invention relates to the field of anti-radiation integrated circuit design, especially designed to use two-input protection gates and four-input protection gates to reinforce sequential circuits, and has anti-single event upset (Single event upset, SEU) and partial resistance to multiple-bit upset (Multiple-bit upset, MBU) capabilities. Specifically, it relates to a radiation-resistant latch using a four-input protection gate. Background technique [0002] When integrated circuits are used in the space field, they will be bombarded by particles to cause soft errors. Common radiation mechanisms in space include the bombardment of alpha particles, high-energy neutrons, high-energy cosmic rays, and low-energy cosmic neutrons. These particles hit the silicon surface and cause transistors Incorrect turn-on or turn-off due to excess charge generated internally. For digital circuits used in space environments, especially sequential circuits, the occurre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/094
Inventor 姚素英闫茜聂凯明史再峰徐江涛高志远
Owner TIANJIN UNIV
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