Method for packaging semiconductor chip
A chip packaging and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting packaging quality, low glass transition temperature, high temperature and high pressure resistance, etc., to achieve the effect of improving strength
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[0025] The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.
[0026] like figure 1 As shown, in one embodiment of the present invention, the semiconductor chip package structure includes a PPTC substrate 10 , and the PPTC substrate 10 includes an upper surface and a lower surface opposite to the upper surface. The PPTC substrate 10 is composed of multiple single-layer PCT boards. The upper surface of the PPTC substrate 10 is covered with a first insulating layer 11 , and the lower surface of the PPTC substrate 10 is covered with a second insulating layer 12 .
[0027] The diode 20 has a first electrode surface 21 and a second electrode surface 22 opposite to th...
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