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An On-chip Network Illegal Path Fault Online Error Detection Circuit

An on-chip network and path failure technology, applied in data exchange networks, electrical components, digital transmission systems, etc., can solve problems such as reducing network operation efficiency, and achieve the effect of reducing complexity, reducing cost and cost, and reducing hardware resources

Inactive Publication Date: 2017-07-18
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, its disadvantage is that before each forwarding, it is necessary to obtain prior information on whether each router on the relevant path is faulty, and then select an appropriate path for the data packet to bypass the faulty router.
This method greatly reduces the operating efficiency of the network and is not suitable for high-speed on-chip networks

Method used

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  • An On-chip Network Illegal Path Fault Online Error Detection Circuit
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  • An On-chip Network Illegal Path Fault Online Error Detection Circuit

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Embodiment Construction

[0071] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, but the protection scope of the present invention is not limited to the following description.

[0072] An on-chip network illegal path fault online error detection circuit is arranged on each receiving port of the network-on-chip router at all levels, and it includes a label update unit and a fault error detection unit;

[0073] The label update unit corresponds to different input ports of the network-on-chip router at the current level, and updates the network-on-chip packet header to record the identifier of the input port of the previous hop route, and provides the input port of the network-on-chip router at the current level for the next-hop error detection unit information;

[0074] The fault detection unit is used to identify faults, and judge whether the network-on-chip data packet received at the input...

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Abstract

The invention discloses an on-chip network illegal path fault online error detection circuit, which is arranged on each receiving port of the on-chip network router, and a label update unit corresponds to different input ports of the on-chip network router, and updates the header part of the on-chip network data packet for Record the identifier of the input port of the previous hop route, and provide the input terminal information of the network-on-chip router at the next hop for the next-hop error detection unit; the fault error detection unit judges according to the relative position information of the data packet destination and the current data packet Whether the network-on-chip data packet received at the input end of the network-on-chip router is affected by the failure of the control path of the previous hop network-on-chip router, and is sent to a wrong port, resulting in an illegal path. The invention can effectively identify data packets forwarded in the wrong direction and generating illegal paths due to control logic errors. The present invention makes full use of the existing computing resources in the router, and can also process in parallel with the normal flow of the router without affecting the performance of the router.

Description

technical field [0001] The invention relates to fault detection of a two-dimensional on-chip network router, in particular to an on-chip network illegal path fault on-line error detection circuit. Background technique [0002] The commonly used two-dimensional network-on-chip router architecture with virtual channels is shown in Figure 1, which includes five input and output physical ports of east, south, west, north and local interfaces, as shown in Figure 2. In addition to the local interface, each other input port can contain several virtual channels (virtual channel, VC). This router contains 5 processing steps, namely routing computation (routing computation, RC), virtual channel president (virtual channel allocator, VA), switching arbitration (switch allocation, SA), switching transmission (switch traversal, ST) and output transmission (linktraversal, LT). Among them, the routing calculation unit unpacks the input data packet, analyzes the source address and destinat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/24H04L12/26
Inventor 张晓帆黄乐天王君实
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA